From patchwork Mon Jun 6 19:24:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "J. Mayer" X-Patchwork-Id: 631104 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rNlF34Z0mz9t4Z for ; Tue, 7 Jun 2016 05:31:34 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Io3dfK3w; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:in-reply-to:references :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=yOr+wbeIeB2nP5DfCXNfQzI0kHfyMk818YjH0h/BZi717P3qk4Fg+ lQJD1WCv/ruDWioEQPU8oQMiHNb/VNjHrVgYiNF3ObVSxsYifxOcNO+pYqZKUeKf LPRaTKuyAGoJvxAqaJkr8GHZY7iZDzCEjkLd7X2TJgIVLjzIm+uz3w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=default; bh=Hkdy6k/2VzyXDYlRQ7lsX6CIzB4=; b=Io3dfK3wbZKKa1NzxinwRANB1+n7 D26Qjk9VUJSrWZ4lyuqzE4p0IDjsacfyUnuIvxoZdT0WsLwqgOQYeHf5F91d0FNS aAzC5AbS0/x1aPsPvuq8vvIEfLNoYNhEgedl/Lynho9X+JizdQTFa29VDF63oOeV fGmoh5BS83j7uQM= Received: (qmail 44174 invoked by alias); 6 Jun 2016 19:24:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 44159 invoked by uid 89); 6 Jun 2016 19:24:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.4 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 spammy=H*r:rev.sfr.net, dual, Dual, Hx-languages-length:2484 X-HELO: smtp26.services.sfr.fr Received: from smtp26.services.sfr.fr (HELO smtp26.services.sfr.fr) (93.17.128.20) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 06 Jun 2016 19:24:51 +0000 Received: from rapid.plaine (133.220.145.77.rev.sfr.net [77.145.220.133]) by msfrf2629.sfr.fr (SMTP Server) with ESMTP id E06CB1C001045; Mon, 6 Jun 2016 21:24:47 +0200 (CEST) Received: from rapid.plaine (133.220.145.77.rev.sfr.net [77.145.220.133]) by msfrf2629.sfr.fr (SMTP Server) with ESMTP; Mon, 6 Jun 2016 21:24:45 +0200 (CEST) Message-ID: <1465241090.11250.131.camel@magic.fr> Subject: Re: [PATCH, i386] Add native support for VIA C7, Eden and Nano CPUs From: "J. Mayer" To: Joseph Myers Cc: "gcc-patches@gcc.gnu.org" Date: Mon, 06 Jun 2016 21:24:50 +0200 In-Reply-To: References: <1464808504.11250.36.camel@magic.fr> Mime-Version: 1.0 X-sfr-mailing: LEGIT On Mon, 2016-06-06 at 17:27 +0000, Joseph Myers wrote: > This patch is missing the invoke.texi changes to document all the new > CPU  > names. Hi, correct, please consider adding the following patch to fix this. Regards. --- SSE4.1 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-x4 +VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. +(No scheduling is implemented for this chip.) +  @item geode  AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.  @end table diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ce162a0..ac7f8a8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -23261,6 +23261,54 @@ VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support.  (No scheduling is  implemented for this chip.)   +@item c7 +VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item samuel-2 +VIA Eden Samuel 2 CPU with MMX and 3DNow!@: instruction set support. +(No scheduling is implemented for this chip.) + +@item nehemiah +VIA Eden Nehemiah CPU with MMX and SSE instruction set support. +(No scheduling is implemented for this chip.) + +@item esther +VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item eden-x2 +VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item eden-x4 +VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano +Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-1000 +VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-2000 +VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-3000 +VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. +(No scheduling is implemented for this chip.) + +@item nano-x2 +VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and