From patchwork Fri Apr 29 09:21:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 616662 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qx7Wk0sYGz9t3l for ; Fri, 29 Apr 2016 19:22:24 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=dK2DHlHo; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id; q=dns; s=default; b=QFrVKY/AOQgy0Q7 68+x0wWjIfHlWh1c9aLuCKns5dCF84BTIK2yIcMTpASjuNKde+mRpiFaNElLhN8z Mtc53WNkuhdSmqAQxKIDCPuLC0VI89kTZEp2lOiAQK7A5r0rxaYrjuKsFGSSFNXH dmZw9WyhB3yzFpk2UaFl3rWHMbpE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id; s=default; bh=Y9l6OXzVsLUN/TCeulzrw yOS6DU=; b=dK2DHlHoI/7IgsXTQv+8SPoSHjaUhUUMx5jEhC2LnCQbd9hVVX+uT HEOWWOUZYuAEmk2rhd068SqTYtDeaiYlvp+mTuMxla4TsRUaG+p1o+G5t6jpLepN sD1IZXGbgV+872UctGzc4Sec6IulCT/yQWx4RYCMzYbbsN9JPljPQs= Received: (qmail 23267 invoked by alias); 29 Apr 2016 09:22:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 23248 invoked by uid 89); 29 Apr 2016 09:22:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.8 required=5.0 tests=BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=mlg, stm, const0_operand, ddd X-HELO: e06smtp12.uk.ibm.com Received: from e06smtp12.uk.ibm.com (HELO e06smtp12.uk.ibm.com) (195.75.94.108) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Fri, 29 Apr 2016 09:22:01 +0000 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 29 Apr 2016 10:21:55 +0100 X-IBM-Helo: d06dlp03.portsmouth.uk.ibm.com X-IBM-MailFrom: krebbel@linux.vnet.ibm.com X-IBM-RcptTo: gcc-patches@gcc.gnu.org Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id 9F9571B0804B for ; Fri, 29 Apr 2016 10:22:42 +0100 (BST) Received: from d06av03.portsmouth.uk.ibm.com (d06av03.portsmouth.uk.ibm.com [9.149.37.213]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u3T9Ls486750718 for ; Fri, 29 Apr 2016 09:21:54 GMT Received: from d06av03.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av03.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u3T9Ls07032055 for ; Fri, 29 Apr 2016 03:21:54 -0600 Received: from maggie.ibm.com (icon-9-164-179-89.megacenter.de.ibm.com [9.164.179.89]) by d06av03.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u3T9LrVP032032 (version=TLSv1/SSLv3 cipher=AES256-SHA256 bits=256 verify=NO) for ; Fri, 29 Apr 2016 03:21:53 -0600 From: Andreas Krebbel To: gcc-patches@gcc.gnu.org Subject: [Committed] S/390: Memory constraint cleanup Date: Fri, 29 Apr 2016 11:21:52 +0200 Message-Id: <1461921712-30633-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16042909-0009-0000-0000-0000165C1A89 X-IsSubscribed: yes This fixes an issue with the long displacement memory address constraints S and T. These were defined to only accept long displacement addresses. This is wrong since a memory constraint must not reject an address with a 0 displacement. Reload relies on being able to turn an invalid memory address into a valid one by reloading the address into a base register. The S and T constraints would reject such an address. This isn't really a problem for the backend since we used the constraints with that knowledge there but it is a problem for people writing inline assemblies. gcc/ChangeLog: 2016-04-29 Ulrich Weigand * config/s390/constraints.md ("U", "W"): Invoke s390_mem_constraint with "ZR" and "ZT". * config/s390/s390.c (s390_check_qrst_address): Reject invalid addresses when using LRA. Accept also short displacements for S and T constraints. Do not check for long displacement target for S and T constraints. (s390_mem_constraint): Remove handling of U and W constraints. * config/s390/s390.md (various patterns): Remove the short displacement constraints (Q and R) if a long displacement constraint is present. Add longdisp as required CPU capability. * config/s390/vector.md: Likewise. * config/s390/vx-builtins.md: Likewise. --- gcc/ChangeLog | 15 ++ gcc/config/s390/constraints.md | 15 +- gcc/config/s390/s390.c | 31 ++-- gcc/config/s390/s390.md | 401 ++++++++++++++++++++++------------------- gcc/config/s390/vector.md | 36 ++-- gcc/config/s390/vx-builtins.md | 6 +- 6 files changed, 274 insertions(+), 230 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 984a703..6e783c8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2016-04-29 Ulrich Weigand + + * config/s390/constraints.md ("U", "W"): Invoke + s390_mem_constraint with "ZR" and "ZT". + * config/s390/s390.c (s390_check_qrst_address): Reject invalid + addresses when using LRA. Accept also short displacements for S + and T constraints. Do not check for long displacement target for + S and T constraints. + (s390_mem_constraint): Remove handling of U and W constraints. + * config/s390/s390.md (various patterns): Remove the short + displacement constraints (Q and R) if a long displacement + constraint is present. Add longdisp as required CPU capability. + * config/s390/vector.md: Likewise. + * config/s390/vx-builtins.md: Likewise. + 2016-04-29 Uros Bizjak * config/i386/i386.md (Load+RegOp to Mov+MemOp peephole2): diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md index 7857700..190cdc9 100644 --- a/gcc/config/s390/constraints.md +++ b/gcc/config/s390/constraints.md @@ -77,8 +77,8 @@ ;; B -- Multiple letter constraint followed by Q, R, S, or T: ;; Memory reference of the type specified by second letter that ;; does *not* refer to a literal pool entry. -;; U -- Pointer with short displacement. (deprecated - use ZQZR) -;; W -- Pointer with long displacement. (deprecated - use ZSZT) +;; U -- Pointer with short displacement. (deprecated - use ZR) +;; W -- Pointer with long displacement. (deprecated - use ZT) ;; Y -- Address style operand without index. ;; ZQ -- Pointer without index register and with short displacement. ;; ZR -- Pointer with index register and short displacement. @@ -455,8 +455,7 @@ ; the TARGET_MEM_CONSTRAINT macro. (define_memory_constraint "m" "Matches the most general memory address for pre-z10 machines." - (match_test "s390_mem_constraint (\"R\", op) - || s390_mem_constraint (\"T\", op)")) + (match_test "s390_mem_constraint (\"T\", op)")) (define_memory_constraint "AQ" "@internal @@ -512,12 +511,12 @@ (define_address_constraint "U" - "Pointer with short displacement. (deprecated - use ZQZR)" - (match_test "s390_mem_constraint (\"U\", op)")) + "Pointer with short displacement. (deprecated - use ZR)" + (match_test "s390_mem_constraint (\"ZR\", op)")) (define_address_constraint "W" - "Pointer with long displacement. (deprecated - use ZSZT)" - (match_test "s390_mem_constraint (\"W\", op)")) + "Pointer with long displacement. (deprecated - use ZT)" + (match_test "s390_mem_constraint (\"ZT\", op)")) (define_address_constraint "ZQ" diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index a1d0930..155be3c 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -3116,6 +3116,19 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) decomposed = true; } + /* With reload, we sometimes get intermediate address forms that are + actually invalid as-is, but we need to accept them in the most + generic cases below ('R' or 'T'), since reload will in fact fix + them up. LRA behaves differently here; we never see such forms, + but on the other hand, we need to strictly reject every invalid + address form. Perform this check right up front. */ + if (lra_in_progress) + { + if (!decomposed && !s390_decompose_address (op, &addr)) + return 0; + decomposed = true; + } + switch (c) { case 'Q': /* no index short displacement */ @@ -3140,25 +3153,17 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) break; case 'S': /* no index long displacement */ - if (!TARGET_LONG_DISPLACEMENT) - return 0; if (!decomposed && !s390_decompose_address (op, &addr)) return 0; if (addr.indx) return 0; - if (s390_short_displacement (addr.disp)) - return 0; break; case 'T': /* with index long displacement */ - if (!TARGET_LONG_DISPLACEMENT) - return 0; /* Any invalid address here will be fixed up by reload, so accept it for the most generic constraint. */ - if ((decomposed || s390_decompose_address (op, &addr)) - && s390_short_displacement (addr.disp)) - return 0; break; + default: return 0; } @@ -3167,7 +3172,7 @@ s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) /* Evaluates constraint strings described by the regular expression - ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for + ([A|B|Z](Q|R|S|T))|Y and returns 1 if OP is a valid operand for the constraint given in STR, or 0 else. */ int @@ -3197,12 +3202,6 @@ s390_mem_constraint (const char *str, rtx op) if (GET_CODE (op) != MEM) return 0; return s390_check_qrst_address (c, XEXP (op, 0), true); - case 'U': - return (s390_check_qrst_address ('Q', op, true) - || s390_check_qrst_address ('R', op, true)); - case 'W': - return (s390_check_qrst_address ('S', op, true) - || s390_check_qrst_address ('T', op, true)); case 'Y': /* Simply check for the basic form of a shift count. Reload will take care of making sure we have a proper base register. */ diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 2b4e8f4..8757470 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -797,6 +797,7 @@ tm\t%S0,%b1 tmy\t%S0,%b1" [(set_attr "op_type" "SI,SIY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super,z10_super")]) (define_insn "*tmdi_reg" @@ -850,7 +851,7 @@ (compare (ashiftrt:DI (ashift:DI - (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) + (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) (const_int 32)) (const_int 32)) (match_operand:DI 1 "const0_operand" ""))) (set (match_operand:DI 2 "register_operand" "=d,d") @@ -865,7 +866,7 @@ ; ltr, lt, ltgr, ltg (define_insn "*tst_extimm" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") + (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") (match_operand:GPR 1 "const0_operand" ""))) (set (match_operand:GPR 2 "register_operand" "=d,d") (match_dup 0))] @@ -879,7 +880,7 @@ ; ltr, lt, ltgr, ltg (define_insn "*tst_cconly_extimm" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") + (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") (match_operand:GPR 1 "const0_operand" ""))) (clobber (match_scratch:GPR 2 "=X,d"))] "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" @@ -912,6 +913,7 @@ icm\t%2,15,%S0 icmy\t%2,15,%S0" [(set_attr "op_type" "RR,RS,RSY") + (set_attr "cpu_facility" "*,*,longdisp") (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) (define_insn "*tstsi_cconly" @@ -925,6 +927,7 @@ icm\t%2,15,%S0 icmy\t%2,15,%S0" [(set_attr "op_type" "RR,RS,RSY") + (set_attr "cpu_facility" "*,*,longdisp") (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) (define_insn "*tstdi_cconly_31" @@ -960,6 +963,7 @@ icmy\t%2,,%S0 tml\t%0," [(set_attr "op_type" "RS,RSY,RI") + (set_attr "cpu_facility" "*,longdisp,*") (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) (define_insn "*tsthiCCT_cconly" @@ -973,6 +977,7 @@ icmy\t%2,3,%S0 tml\t%0,65535" [(set_attr "op_type" "RS,RSY,RI") + (set_attr "cpu_facility" "*,longdisp,*") (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) (define_insn "*tstqiCCT_cconly" @@ -985,6 +990,7 @@ cliy\t%S0,0 tml\t%0,255" [(set_attr "op_type" "SI,SIY,RI") + (set_attr "cpu_facility" "*,longdisp,*") (set_attr "z10prop" "z10_super,z10_super,z10_super")]) (define_insn "*tst" @@ -998,6 +1004,7 @@ icm\t%2,,%S0 icmy\t%2,,%S0" [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*tst_cconly" @@ -1010,6 +1017,7 @@ icm\t%2,,%S0 icmy\t%2,,%S0" [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) @@ -1018,7 +1026,7 @@ (define_insn "*cmpdi_cct" [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") - (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] + (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" "@ cgr\t%0,%1 @@ -1042,6 +1050,7 @@ cy\t%0,%1 #" [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") + (set_attr "cpu_facility" "*,*,*,*,longdisp,*") (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) ; Compare (signed) instructions @@ -1049,7 +1058,7 @@ (define_insn "*cmpdi_ccs_sign" [(set (reg CC_REGNUM) (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" - "d,RT,b")) + "d,T,b")) (match_operand:DI 0 "register_operand" "d, d,d")))] "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" "@ @@ -1072,7 +1081,7 @@ chy\t%0,%1 chrl\t%0,%1" [(set_attr "op_type" "RX,RXY,RIL") - (set_attr "cpu_facility" "*,*,z10") + (set_attr "cpu_facility" "*,longdisp,z10") (set_attr "type" "*,*,larl") (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) @@ -1087,7 +1096,7 @@ (define_insn "*cmpdi_ccs_signhi_rl" [(set (reg CC_REGNUM) - (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) + (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) (match_operand:GPR 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" "@ @@ -1113,7 +1122,7 @@ c\t%0,%1 crl\t%0,%1" [(set_attr "op_type" "RR,RI,SIL,RIL,RX,RXY,RIL") - (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") + (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") (set_attr "type" "*,*,*,*,*,*,larl") (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) @@ -1146,8 +1155,8 @@ (define_insn "*cmpdi_ccu_zero" [(set (reg CC_REGNUM) (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" - "d,RT,b")) - (match_operand:DI 0 "register_operand" "d, d,d")))] + "d,T,b")) + (match_operand:DI 0 "register_operand" "d,d,d")))] "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" "@ clgfr\t%0,%1 @@ -1161,9 +1170,9 @@ (define_insn "*cmpdi_ccu" [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" - "d, d,d,Q, d, Q,BQ") + "d, d,d,Q,d, Q,BQ") (match_operand:DI 1 "general_operand" - "d,Op,b,D,RT,BQ,Q")))] + "d,Op,b,D,T,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" "@ clgr\t%0,%1 @@ -1193,7 +1202,7 @@ # #" [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") - (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") + (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") (set_attr "type" "*,*,larl,*,*,*,*,*") (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) @@ -1210,7 +1219,7 @@ # #" [(set_attr "op_type" "RS,RSY,SIL,SS,SS") - (set_attr "cpu_facility" "*,*,z10,*,*") + (set_attr "cpu_facility" "*,longdisp,z10,*,*") (set_attr "z10prop" "*,*,z10_super,*,*")]) (define_insn "*cmpqi_ccu" @@ -1227,6 +1236,7 @@ # #" [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") + (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) @@ -1426,8 +1436,8 @@ ; FIXME: More constants are possible by enabling jxx, jyy constraints ; for TImode (use double-int for the calculations) (define_insn "movti" - [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o") - (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))] + [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o") + (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dPT,d"))] "TARGET_ZARCH" "@ lmg\t%0,%N0,%S1 @@ -1635,9 +1645,9 @@ (define_insn "*movdi_64" [(set (match_operand:DI 0 "nonimmediate_operand" - "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR") + "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R") (match_operand:DI 1 "general_operand" - " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))] + " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))] "TARGET_ZARCH" "@ lghi\t%0,%h1 @@ -1743,9 +1753,9 @@ (define_insn "*movdi_31" [(set (match_operand:DI 0 "nonimmediate_operand" - "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") + "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") (match_operand:DI 1 "general_operand" - " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] + " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] "!TARGET_ZARCH" "@ lm\t%0,%N0,%S1 @@ -1762,7 +1772,7 @@ #" [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") - (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) + (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) ; For a load from a symbol ref we can use one of the target registers ; together with larl to load the address. @@ -1834,13 +1844,14 @@ (define_insn "*la_64" [(set (match_operand:DI 0 "register_operand" "=d,d") - (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] + (match_operand:QI 1 "address_operand" "ZR,ZT"))] "TARGET_64BIT" "@ la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") (set_attr "type" "la") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_peephole2 @@ -1897,9 +1908,9 @@ (define_insn "*movsi_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" - "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR") + "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") (match_operand:SI 1 "general_operand" - " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))] + " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] "TARGET_ZARCH" "@ lhi\t%0,%h1 @@ -2023,13 +2034,14 @@ (define_insn "*la_31" [(set (match_operand:SI 0 "register_operand" "=d,d") - (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] + (match_operand:QI 1 "address_operand" "ZR,ZT"))] "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" "@ la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") (set_attr "type" "la") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_peephole2 @@ -2058,7 +2070,7 @@ (define_insn "*la_31_and" [(set (match_operand:SI 0 "register_operand" "=d,d") - (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") + (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") (const_int 2147483647)))] "!TARGET_64BIT" "@ @@ -2066,6 +2078,7 @@ lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") (set_attr "type" "la") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_insn_and_split "*la_31_and_cc" @@ -2084,7 +2097,7 @@ (define_insn "force_la_31" [(set (match_operand:SI 0 "register_operand" "=d,d") - (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) + (match_operand:QI 1 "address_operand" "ZR,ZT")) (use (const_int 0))] "!TARGET_64BIT" "@ @@ -2092,6 +2105,7 @@ lay\t%0,%a1" [(set_attr "op_type" "RX") (set_attr "type" "la") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) ; @@ -2117,8 +2131,8 @@ }) (define_insn "*movhi" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR") - (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") + (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] "" "@ lr\t%0,%1 @@ -2138,7 +2152,7 @@ vsteh\t%v1,%0,0" [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") - (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec") + (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vec,vec,vec,vec,vec,vec") (set_attr "z10prop" "z10_fr_E1, z10_fwd_A1, z10_super_E1, @@ -2182,8 +2196,8 @@ }) (define_insn "*movqi" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR") - (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") + (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] "" "@ lr\t%0,%1 @@ -2203,7 +2217,7 @@ vsteb\t%v1,%0,0" [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") - (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec") + (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vec,vec,vec,vec,vec,vec") (set_attr "z10prop" "z10_fr_E1, z10_fwd_A1, z10_super_E1, @@ -2236,6 +2250,7 @@ ic\t%0,%1 icy\t%0,%1" [(set_attr "op_type" "RX,RXY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; @@ -2251,6 +2266,7 @@ icm\t%0,3,%S1 icmy\t%0,3,%S1" [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; @@ -2268,6 +2284,7 @@ ear\t%0,%1" [(set_attr "op_type" "RR,RX,RXY,RRE") (set_attr "type" "lr,load,load,*") + (set_attr "cpu_facility" "*,*,longdisp,*") (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) ; @@ -2281,8 +2298,8 @@ "") (define_insn "*mov_64" - [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") - (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] + [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") + (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] "TARGET_ZARCH" "@ lzxr\t%0 @@ -2400,9 +2417,9 @@ (define_insn "*mov_64dfp" [(set (match_operand:DD_DF 0 "nonimmediate_operand" - "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR") + "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,d,v,R") (match_operand:DD_DF 1 "general_operand" - " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))] + " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,d,v,R,v"))] "TARGET_DFP" "@ lzdr\t%0 @@ -2428,11 +2445,11 @@ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store") (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*") - (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")]) + (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")]) (define_insn "*mov_64" - [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR") - (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))] + [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T,v,v,R") + (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d,v,R,v"))] "TARGET_ZARCH" "@ lzdr\t%0 @@ -2454,13 +2471,13 @@ (set_attr "type" "fsimpdf,fload,fload,fload, fstore,fstore,*,lr,load,load,store,store,*,load,store") (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*") - (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")]) + (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec")]) (define_insn "*mov_31" [(set (match_operand:DD_DF 0 "nonimmediate_operand" - "=f,f,f,f,R,T,d,d,Q,S, d,o") + "=f,f,f,f,R,T,d,d,Q,S, d,o") (match_operand:DD_DF 1 "general_operand" - " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] + " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] "!TARGET_ZARCH" "@ lzdr\t%0 @@ -2478,7 +2495,7 @@ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") (set_attr "type" "fsimpdf,fload,fload,fload, fstore,fstore,lm,lm,stm,stm,*,*") - (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) + (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) (define_split [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") @@ -2527,9 +2544,9 @@ (define_insn "mov" [(set (match_operand:SD_SF 0 "nonimmediate_operand" - "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR") + "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") (match_operand:SD_SF 1 "general_operand" - " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))] + " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] "" "@ lzer\t%0 @@ -2558,7 +2575,7 @@ (set_attr "type" "fsimpsf,fsimpsf,fload,fload,fload,fload, fstore,fstore,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") - (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")]) + (set_attr "cpu_facility" "z196,vec,*,vec,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vec,vec,vec,vec,vec,vec")]) ; ; movcc instruction pattern @@ -2578,6 +2595,7 @@ sty\t%1,%0" [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") (set_attr "type" "lr,*,*,load,load,store,store") + (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) @@ -2701,7 +2719,7 @@ (define_insn "*load_multiple_di" [(match_parallel 0 "load_multiple_operation" [(set (match_operand:DI 1 "register_operand" "=r") - (match_operand:DI 2 "s_operand" "QS"))])] + (match_operand:DI 2 "s_operand" "S"))])] "reload_completed && TARGET_ZARCH" { int words = XVECLEN (operands[0], 0); @@ -2722,6 +2740,7 @@ return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; } [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "type" "lm")]) ; @@ -2791,7 +2810,7 @@ (define_insn "*store_multiple_di" [(match_parallel 0 "store_multiple_operation" - [(set (match_operand:DI 1 "s_operand" "=QS") + [(set (match_operand:DI 1 "s_operand" "=S") (match_operand:DI 2 "register_operand" "r"))])] "reload_completed && TARGET_ZARCH" { @@ -2814,6 +2833,7 @@ return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; } [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "type" "stm")]) ;; @@ -3670,11 +3690,12 @@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*sethighpartdi_64" [(set (match_operand:DI 0 "register_operand" "=d") - (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") + (unspec:DI [(match_operand:BLK 1 "s_operand" "S") (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH" @@ -3692,6 +3713,7 @@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; @@ -3747,7 +3769,7 @@ (define_insn_and_split "*pre_z10_extzv" [(set (match_operand:GPR 0 "register_operand" "=d") - (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") + (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") (match_operand 2 "nonzero_shift_count_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] @@ -3771,7 +3793,7 @@ (define_insn_and_split "*pre_z10_extv" [(set (match_operand:GPR 0 "register_operand" "=d") - (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") + (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") (match_operand 2 "nonzero_shift_count_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] @@ -4070,10 +4092,11 @@ : "stcmy\t%2,%1,%S0"; } [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super,z10_super")]) (define_insn "*insvdi_mem_reghigh" - [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") + [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") (match_operand 1 "const_int_operand" "n") (const_int 0)) (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") @@ -4156,7 +4179,7 @@ (define_insn "*extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] "TARGET_ZARCH" "@ lgfr\t%0,%1 @@ -4200,7 +4223,7 @@ (define_insn "*extendhidi2_extimm" [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] + (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] "TARGET_ZARCH && TARGET_EXTIMM" "@ lghr\t%0,%1 @@ -4213,7 +4236,7 @@ (define_insn "*extendhidi2" [(set (match_operand:DI 0 "register_operand" "=d") - (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] + (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] "TARGET_ZARCH" "lgh\t%0,%1" [(set_attr "op_type" "RXY") @@ -4245,6 +4268,7 @@ lh\t%0,%1 lhy\t%0,%1" [(set_attr "op_type" "RX,RXY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; @@ -4254,7 +4278,7 @@ ; lbr, lgbr, lb, lgb (define_insn "*extendqi2_extimm" [(set (match_operand:GPR 0 "register_operand" "=d,d") - (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] + (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] "TARGET_EXTIMM" "@ lbr\t%0,%1 @@ -4265,7 +4289,7 @@ ; lb, lgb (define_insn "*extendqi2" [(set (match_operand:GPR 0 "register_operand" "=d") - (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] + (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" "lb\t%0,%1" [(set_attr "op_type" "RXY") @@ -4310,7 +4334,7 @@ (define_insn "*zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] "TARGET_ZARCH" "@ llgfr\t%0,%1 @@ -4327,7 +4351,7 @@ (define_insn "*llgt_sidi" [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) (const_int 2147483647)))] "TARGET_ZARCH" "llgt\t%0,%1" @@ -4336,7 +4360,7 @@ (define_insn_and_split "*llgt_sidi_split" [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) (const_int 2147483647))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH" @@ -4349,7 +4373,7 @@ (define_insn "*llgt_sisi" [(set (match_operand:SI 0 "register_operand" "=d,d") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") + (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") (const_int 2147483647)))] "TARGET_ZARCH" "@ @@ -4423,7 +4447,7 @@ ; llhrl, llghrl (define_insn "*zero_extendhi2_z10" [(set (match_operand:GPR 0 "register_operand" "=d,d,d") - (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] + (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] "TARGET_Z10" "@ llhr\t%0,%1 @@ -4437,7 +4461,7 @@ ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc (define_insn "*zero_extend2_extimm" [(set (match_operand:GPR 0 "register_operand" "=d,d") - (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] + (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] "TARGET_EXTIMM" "@ llr\t%0,%1 @@ -4448,7 +4472,7 @@ ; llgh, llgc (define_insn "*zero_extend2" [(set (match_operand:GPR 0 "register_operand" "=d") - (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] + (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llg\t%0,%1" [(set_attr "op_type" "RXY") @@ -4456,7 +4480,7 @@ (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") - (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) + (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH" "#" @@ -4469,7 +4493,7 @@ (define_insn_and_split "*zero_extendqisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") - (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] + (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] "!TARGET_ZARCH" "#" "&& reload_completed" @@ -4493,7 +4517,7 @@ (define_insn "*zero_extendqihi2_64" [(set (match_operand:HI 0 "register_operand" "=d") - (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] + (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llgc\t%0,%1" [(set_attr "op_type" "RXY") @@ -4501,7 +4525,7 @@ (define_insn_and_split "*zero_extendqihi2_31" [(set (match_operand:HI 0 "register_operand" "=&d") - (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] + (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] "!TARGET_ZARCH" "#" "&& reload_completed" @@ -5213,7 +5237,7 @@ (define_insn "*adddi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) + (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) (match_operand:DI 1 "register_operand" "0,0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH" @@ -5225,7 +5249,7 @@ (define_insn "*adddi3_zero_cc" [(set (reg CC_REGNUM) - (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) + (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") @@ -5239,7 +5263,7 @@ (define_insn "*adddi3_zero_cconly" [(set (reg CC_REGNUM) - (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) + (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] @@ -5252,7 +5276,7 @@ (define_insn "*adddi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) + (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) (match_operand:DI 1 "register_operand" "0,0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH" @@ -5342,6 +5366,7 @@ ah\t%0,%2 ahy\t%0,%2" [(set_attr "op_type" "RX,RXY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z196prop" "z196_cracked,z196_cracked")]) ; @@ -5350,9 +5375,9 @@ ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi (define_insn "*add3" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") - (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") - (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") + (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") + (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) (clobber (reg:CC CC_REGNUM))] "" "@ @@ -5366,7 +5391,7 @@ a\t%0,%2 asi\t%0,%c2" [(set_attr "op_type" "RR,RRF,RI,RIE,RIL,RIL,RX,RXY,SIY") - (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") + (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, z10_super_E1,z10_super_E1,z10_super_E1")]) @@ -5389,7 +5414,7 @@ al\t%0,%2 alsi\t%0,%c2" [(set_attr "op_type" "RR,RRF,RIL,RIL,RIE,RX,RXY,SIY") - (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") + (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, z10_super_E1,z10_super_E1,z10_super_E1")]) @@ -5407,16 +5432,16 @@ al\t%0,%2 al\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik (define_insn "*add3_carry2_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") - (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") + (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) (match_dup 2))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL1mode)" "@ @@ -5429,7 +5454,7 @@ al\t%0,%2 alsi\t%0,%c2" [(set_attr "op_type" "RR,RRF,RIL,RIL,RIE,RX,RXY,SIY") - (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") + (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, z10_super_E1,z10_super_E1,z10_super_E1")]) @@ -5447,16 +5472,16 @@ al\t%0,%2 al\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik (define_insn "*add3_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") - (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) + (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") + (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) (const_int 0))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode)" "@ @@ -5469,7 +5494,7 @@ al\t%0,%2 alsi\t%0,%c2" [(set_attr "op_type" "RR,RRF,RIL,RIL,RIE,RX,RXY,SIY") - (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") + (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, *,z10_super_E1,z10_super_E1,z10_super_E1")]) @@ -5487,7 +5512,7 @@ al\t%0,%2 al\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) ; alr, al, aly, algr, alg, alrk, algrk @@ -5503,16 +5528,16 @@ al\t%0,%2 al\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) ; ahi, afi, aghi, agfi, asi, agsi (define_insn "*add3_imm_cc" [(set (reg CC_REGNUM) (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") - (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) + (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) (const_int 0))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") + (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCAmode) && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") @@ -5704,7 +5729,7 @@ (define_insn "*subdi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") - (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) + (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH" "@ @@ -5717,7 +5742,7 @@ (define_insn "*subdi3_zero_cc" [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") - (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) + (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] @@ -5731,7 +5756,7 @@ (define_insn "*subdi3_zero_cconly" [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") - (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) + (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" @@ -5744,7 +5769,7 @@ (define_insn "*subdi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") - (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) + (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH" "@ @@ -5832,6 +5857,7 @@ sh\t%0,%2 shy\t%0,%2" [(set_attr "op_type" "RX,RXY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z196prop" "z196_cracked,z196_cracked")]) ; @@ -5851,7 +5877,7 @@ s\t%0,%2 s\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg, slrk, slgrk @@ -5869,7 +5895,7 @@ sl\t%0,%2 sl\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg, slrk, slgrk @@ -5886,7 +5912,7 @@ sl\t%0,%2 sl\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg, slrk, slgrk @@ -5904,7 +5930,7 @@ sl\t%0,%2 sl\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg, slrk, slgrk @@ -5921,7 +5947,7 @@ sl\t%0,%2 sl\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg, slrk, slgrk @@ -5938,7 +5964,7 @@ sl\t%0,%2 sl\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) @@ -5955,7 +5981,7 @@ sl\t%0,%2 sl\t%0,%2" [(set_attr "op_type" "RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,*,longdisp") (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) @@ -6033,7 +6059,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,RT")) + (match_operand:GPR 2 "general_operand" "d,T")) (match_dup 1))) (set (match_operand:GPR 0 "register_operand" "=d,d") (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] @@ -6050,7 +6076,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,RT")) + (match_operand:GPR 2 "general_operand" "d,T")) (match_dup 1))) (clobber (match_scratch:GPR 0 "=d,d"))] "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" @@ -6068,7 +6094,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,RT")) + (match_operand:GPR 2 "general_operand" "d,T")) (match_dup 2))) (set (match_operand:GPR 0 "register_operand" "=d,d") (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] @@ -6084,7 +6110,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,RT")) + (match_operand:GPR 2 "general_operand" "d,T")) (match_dup 2))) (clobber (match_scratch:GPR 0 "=d,d"))] "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" @@ -6099,7 +6125,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,RT")) + (match_operand:GPR 2 "general_operand" "d,T")) (const_int 0))) (set (match_operand:GPR 0 "register_operand" "=d,d") (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] @@ -6114,7 +6140,7 @@ [(set (match_operand:GPR 0 "register_operand" "=d,d") (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,RT"))) + (match_operand:GPR 2 "general_operand" "d,T"))) (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "@ @@ -6127,7 +6153,7 @@ [(set (reg CC_REGNUM) (compare (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") - (match_operand:GPR 2 "general_operand" "d,RT")) + (match_operand:GPR 2 "general_operand" "d,T")) (match_operand:GPR 3 "s390_slb_comparison" "")) (const_int 0))) (set (match_operand:GPR 0 "register_operand" "=d,d") @@ -6143,7 +6169,7 @@ (define_insn "*sub3_slb" [(set (match_operand:GPR 0 "register_operand" "=d,d") (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") - (match_operand:GPR 2 "general_operand" "d,RT")) + (match_operand:GPR 2 "general_operand" "d,T")) (match_operand:GPR 3 "s390_slb_comparison" ""))) (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" @@ -6255,13 +6281,13 @@ ; locr, loc, stoc, locgr, locg, stocg (define_insn_and_split "*movcc" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,S,S,&d") (if_then_else:GPR (match_operator 1 "s390_comparison" - [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") + [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c") (match_operand 5 "const_int_operand" "")]) - (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") - (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] + (match_operand:GPR 3 "nonimmediate_operand" " d,0,S,0,d,0,S") + (match_operand:GPR 4 "nonimmediate_operand" " 0,d,0,S,0,d,S")))] "TARGET_Z196" "@ locr%C1\t%0,%3 @@ -6296,7 +6322,7 @@ (define_insn "*muldi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") - (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) + (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) (match_operand:DI 1 "register_operand" "0,0")))] "TARGET_ZARCH" "@ @@ -6308,7 +6334,7 @@ (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] + (match_operand:DI 2 "general_operand" "d,K,T,Os")))] "TARGET_ZARCH" "@ msgr\t%0,%2 @@ -6348,7 +6374,7 @@ msfi\t%0,%2" [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") - (set_attr "cpu_facility" "*,*,*,*,z10")]) + (set_attr "cpu_facility" "*,*,*,longdisp,z10")]) ; ; mulsidi3 instruction pattern(s). @@ -6375,11 +6401,11 @@ ; mlr, ml, mlgr, mlg (define_insn "umul3" - [(set (match_operand:DW 0 "register_operand" "=d, d") + [(set (match_operand:DW 0 "register_operand" "=d,d") (mult:DW (zero_extend:DW - (match_operand: 1 "register_operand" "%0, 0")) + (match_operand: 1 "register_operand" "%0,0")) (zero_extend:DW - (match_operand: 2 "nonimmediate_operand" " d,RT"))))] + (match_operand: 2 "nonimmediate_operand" " d,T"))))] "TARGET_CPU_ZARCH" "@ mlr\t%0,%2 @@ -6479,7 +6505,7 @@ (ashift:TI (zero_extend:TI (mod:DI (match_operand:DI 1 "register_operand" "0,0") - (match_operand:DI 2 "general_operand" "d,RT"))) + (match_operand:DI 2 "general_operand" "d,T"))) (const_int 64)) (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] "TARGET_ZARCH" @@ -6496,7 +6522,7 @@ (zero_extend:TI (mod:DI (match_operand:DI 1 "register_operand" "0,0") (sign_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) + (match_operand:SI 2 "nonimmediate_operand" "d,T")))) (const_int 64)) (zero_extend:TI (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] @@ -6555,7 +6581,7 @@ (truncate:DI (umod:TI (match_operand:TI 1 "register_operand" "0,0") (zero_extend:TI - (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) + (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) (const_int 64)) (zero_extend:TI (truncate:DI @@ -6673,7 +6699,7 @@ (truncate:SI (umod:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) + (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) (const_int 32)) (zero_extend:DI (truncate:SI @@ -6897,10 +6923,10 @@ (define_insn "*anddi3_cc" [(set (reg CC_REGNUM) (compare - (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") - (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) + (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") + (match_operand:DI 2 "general_operand" " d,d,T,NxxDq")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d,d, d, d") + (set (match_operand:DI 0 "register_operand" "=d,d,d, d") (and:DI (match_dup 1) (match_dup 2)))] "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" "@ @@ -6915,10 +6941,10 @@ (define_insn "*anddi3_cconly" [(set (reg CC_REGNUM) (compare - (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") - (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) + (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") + (match_operand:DI 2 "general_operand" " d,d,T,NxxDq")) (const_int 0))) - (clobber (match_scratch:DI 0 "=d,d, d, d"))] + (clobber (match_scratch:DI 0 "=d,d,d, d"))] "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode) /* Do not steal TM patterns. */ @@ -6934,12 +6960,12 @@ (define_insn "*anddi3" [(set (match_operand:DI 0 "nonimmediate_operand" - "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") + "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") (and:DI (match_operand:DI 1 "nonimmediate_operand" - "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") + "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") (match_operand:DI 2 "general_operand" - "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) + "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDq,NxQDF,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ @@ -7037,7 +7063,7 @@ ny\t%0,%2 risbg\t%0,%1,%t2,128+%f2,0" [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") - (set_attr "cpu_facility" "*,*,z196,*,*,z10") + (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, z10_super_E1,z10_super_E1,z10_super_E1")]) @@ -7060,7 +7086,7 @@ ny\t%0,%2 risbg\t%0,%1,%t2,128+%f2,0" [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") - (set_attr "cpu_facility" "*,*,z196,*,*,z10") + (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, z10_super_E1,z10_super_E1,z10_super_E1")]) @@ -7087,7 +7113,7 @@ # #" [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") - (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") + (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") (set_attr "z10prop" "*, *, z10_super_E1, @@ -7189,7 +7215,7 @@ niy\t%S0,%b2 #" [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") - (set_attr "cpu_facility" "*,z196,*,*,*,*") + (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) (define_insn "*andqi3_esa" @@ -7283,10 +7309,10 @@ (define_insn "*iordi3_cc" [(set (reg CC_REGNUM) - (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") - (match_operand:DI 2 "general_operand" " d,d,RT")) + (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") + (match_operand:DI 2 "general_operand" " d,d,T")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d,d, d") + (set (match_operand:DI 0 "register_operand" "=d,d,d") (ior:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ @@ -7300,7 +7326,7 @@ (define_insn "*iordi3_cconly" [(set (reg CC_REGNUM) (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") - (match_operand:DI 2 "general_operand" " d,d,RT")) + (match_operand:DI 2 "general_operand" " d,d,T")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" @@ -7314,11 +7340,11 @@ (define_insn "*iordi3" [(set (match_operand:DI 0 "nonimmediate_operand" - "=d, d, d, d, d, d,d,d, d, AQ,Q") + "=d, d, d, d, d, d,d,d,d, AQ,Q") (ior:DI (match_operand:DI 1 "nonimmediate_operand" - " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") + " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") (match_operand:DI 2 "general_operand" - "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) + "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ @@ -7376,7 +7402,7 @@ o\t%0,%2 oy\t%0,%2" [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "cpu_facility" "*,*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) (define_insn "*iorsi3_cconly" @@ -7393,7 +7419,7 @@ o\t%0,%2 oy\t%0,%2" [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "cpu_facility" "*,*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) (define_insn "*iorsi3_zarch" @@ -7413,7 +7439,7 @@ # #" [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") - (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") + (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") (set_attr "z10prop" "z10_super_E1, z10_super_E1, z10_super_E1, @@ -7509,7 +7535,7 @@ oiy\t%S0,%b2 #" [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") - (set_attr "cpu_facility" "*,z196,*,*,*,*") + (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, z10_super,z10_super,*")]) @@ -7619,10 +7645,10 @@ (define_insn "*xordi3_cc" [(set (reg CC_REGNUM) - (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") - (match_operand:DI 2 "general_operand" " d,d,RT")) + (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") + (match_operand:DI 2 "general_operand" " d,d,T")) (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d,d, d") + (set (match_operand:DI 0 "register_operand" "=d,d,d") (xor:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ @@ -7635,10 +7661,10 @@ (define_insn "*xordi3_cconly" [(set (reg CC_REGNUM) - (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") - (match_operand:DI 2 "general_operand" " d,d,RT")) + (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") + (match_operand:DI 2 "general_operand" " d,d,T")) (const_int 0))) - (clobber (match_scratch:DI 0 "=d,d, d"))] + (clobber (match_scratch:DI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" "@ xgr\t%0,%2 @@ -7649,9 +7675,9 @@ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) (define_insn "*xordi3" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") - (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") - (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) + [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") + (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") + (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ @@ -7696,7 +7722,7 @@ x\t%0,%2 xy\t%0,%2" [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "cpu_facility" "*,*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, z10_super_E1,z10_super_E1")]) @@ -7714,7 +7740,7 @@ x\t%0,%2 xy\t%0,%2" [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") - (set_attr "cpu_facility" "*,*,z196,*,*") + (set_attr "cpu_facility" "*,*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, z10_super_E1,z10_super_E1")]) @@ -7733,7 +7759,7 @@ # #" [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") - (set_attr "cpu_facility" "*,*,z196,*,*,*,*") + (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, z10_super_E1,z10_super_E1,*,*")]) @@ -7795,7 +7821,7 @@ xiy\t%S0,%b2 #" [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") - (set_attr "cpu_facility" "*,*,z196,*,*,*") + (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) @@ -8778,8 +8804,8 @@ ; clrt, clgrt, clfit, clgit, clt, clgt (define_insn "*cmp_and_trap_unsigned_int" [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" - [(match_operand:GPR 1 "register_operand" "d,d, d") - (match_operand:GPR 2 "general_operand" "d,D,RT")]) + [(match_operand:GPR 1 "register_operand" "d,d,d") + (match_operand:GPR 2 "general_operand" "d,D,T")]) (const_int 0))] "TARGET_Z10" "@ @@ -8793,7 +8819,7 @@ ; lat, lgat (define_insn "*load_and_trap" - [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") + [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") (const_int 0)) (const_int 0)) (set (match_operand:GPR 1 "register_operand" "=d") @@ -9092,7 +9118,7 @@ (if_then_else (ne (match_operand:SI 1 "register_operand" "d") (const_int 1)) - (match_operand 0 "address_operand" "ZQZR") + (match_operand 0 "address_operand" "ZR") (pc))) (set (match_operand:SI 2 "register_operand" "=1") (plus:SI (match_dup 1) (const_int -1))) @@ -9204,7 +9230,7 @@ ; (define_insn "indirect_jump" - [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] + [(set (pc) (match_operand 0 "address_operand" "ZR"))] "" { if (get_attr_op_type (insn) == OP_TYPE_RR) @@ -9223,7 +9249,7 @@ ; (define_insn "casesi_jump" - [(set (pc) (match_operand 0 "address_operand" "ZQZR")) + [(set (pc) (match_operand 0 "address_operand" "ZR")) (use (label_ref (match_operand 1 "" "")))] "" { @@ -9447,7 +9473,7 @@ (set_attr "z196prop" "z196_cracked")]) (define_insn "*basr" - [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) + [(call (mem:QI (match_operand 0 "address_operand" "ZR")) (match_operand 1 "const_int_operand" "n")) (clobber (match_operand 2 "register_operand" "=r"))] "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" @@ -9508,7 +9534,7 @@ (define_insn "*basr_r" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) + (call (mem:QI (match_operand 1 "address_operand" "ZR")) (match_operand 2 "const_int_operand" "n"))) (clobber (match_operand 3 "register_operand" "=r"))] "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" @@ -9549,7 +9575,7 @@ (define_insn "*tls_load_64" [(set (match_operand:DI 0 "register_operand" "=d") - (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") + (unspec:DI [(match_operand:DI 1 "memory_operand" "T") (match_operand:DI 2 "" "")] UNSPEC_TLS_LOAD))] "TARGET_64BIT" @@ -9568,6 +9594,7 @@ ly\t%0,%1%J2" [(set_attr "op_type" "RX,RXY") (set_attr "type" "load") + (set_attr "cpu_facility" "*,longdisp") (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) (define_insn "*bras_tls" @@ -9600,7 +9627,7 @@ (define_insn "*basr_tls" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) + (call (mem:QI (match_operand 1 "address_operand" "ZR")) (match_operand 2 "const_int_operand" "n"))) (clobber (match_operand 3 "register_operand" "=r")) (use (match_operand 4 "" ""))] @@ -9704,11 +9731,12 @@ ld\t%0,%1 ldy\t%0,%1" [(set_attr "op_type" "RS,RSY,RS,RSY") + (set_attr "cpu_facility" "*,longdisp,*,longdisp") (set_attr "type" "lm,lm,floaddf,floaddf")]) (define_insn "atomic_loadti_1" [(set (match_operand:TI 0 "register_operand" "=r") - (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] + (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] UNSPEC_MOVA))] "TARGET_ZARCH" "lpq\t%0,%1" @@ -9750,10 +9778,11 @@ std %1,%0 stdy %1,%0" [(set_attr "op_type" "RS,RSY,RS,RSY") + (set_attr "cpu_facility" "*,longdisp,*,longdisp") (set_attr "type" "stm,stm,fstoredf,fstoredf")]) (define_insn "atomic_storeti_1" - [(set (match_operand:TI 0 "memory_operand" "=RT") + [(set (match_operand:TI 0 "memory_operand" "=T") (unspec:TI [(match_operand:TI 1 "register_operand" "r")] UNSPEC_MOVA))] "TARGET_ZARCH" @@ -9834,7 +9863,7 @@ ; cdsg, csg (define_insn "*atomic_compare_and_swap_1" [(set (match_operand:TDI 0 "register_operand" "=r") - (match_operand:TDI 1 "memory_operand" "+QS")) + (match_operand:TDI 1 "memory_operand" "+S")) (set (match_dup 1) (unspec_volatile:TDI [(match_dup 1) @@ -9865,6 +9894,7 @@ cds\t%0,%3,%S1 cdsy\t%0,%3,%S1" [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "type" "sem")]) ; cs, csy @@ -9884,6 +9914,7 @@ cs\t%0,%3,%S1 csy\t%0,%3,%S1" [(set_attr "op_type" "RS,RSY") + (set_attr "cpu_facility" "*,longdisp") (set_attr "type" "sem")]) ; @@ -9911,7 +9942,7 @@ ; lan, lang, lao, laog, lax, laxg, laa, laag (define_insn "atomic_fetch__iaf" [(set (match_operand:GPR 0 "register_operand" "=d") - (match_operand:GPR 1 "memory_operand" "+QS")) + (match_operand:GPR 1 "memory_operand" "+S")) (set (match_dup 1) (unspec_volatile:GPR [(ATOMIC_Z196:GPR (match_dup 1) @@ -10402,9 +10433,9 @@ ; (define_insn "prefetch" - [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") - (match_operand:SI 1 "const_int_operand" " n,n") - (match_operand:SI 2 "const_int_operand" " n,n"))] + [(prefetch (match_operand 0 "address_operand" "ZT,X") + (match_operand:SI 1 "const_int_operand" " n,n") + (match_operand:SI 2 "const_int_operand" " n,n"))] "TARGET_Z10" { switch (which_alternative) @@ -10435,8 +10466,8 @@ ; FIXME: There is also mvcin but we cannot use it since src and target ; may overlap. (define_insn "bswap2" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,RT") - (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))] + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") + (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] "TARGET_CPU_ZARCH" "@ lrvr\t%0,%1 @@ -10447,8 +10478,8 @@ (set_attr "z10prop" "z10_super")]) (define_insn "bswaphi2" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d, d,RT") - (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") + (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] "TARGET_CPU_ZARCH" "@ # @@ -10798,7 +10829,7 @@ ; Non-transactional store (define_insn "ntstg" - [(set (match_operand:DI 0 "memory_operand" "=RT") + [(set (match_operand:DI 0 "memory_operand" "=T") (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] UNSPECV_NTSTG))] "TARGET_HTM" @@ -10844,7 +10875,7 @@ (define_insn "lcbb" [(set (match_operand:SI 0 "register_operand" "=d") - (unspec:SI [(match_operand 1 "address_operand" "ZQZR") + (unspec:SI [(match_operand 1 "address_operand" "ZR") (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) (clobber (reg:CC CC_REGNUM))] "TARGET_Z13" diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 5b3cdaf..979cb29 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -137,8 +137,8 @@ ; Full HW vector size moves (define_insn "mov" - [(set (match_operand:V_128 0 "nonimmediate_operand" "=v, v,QR, v, v, v, v, v,v,d") - (match_operand:V_128 1 "general_operand" " v,QR, v,j00,jm1,jyy,jxx,jKK,d,v"))] + [(set (match_operand:V_128 0 "nonimmediate_operand" "=v,v,R, v, v, v, v, v,v,d") + (match_operand:V_128 1 "general_operand" " v,R,v,j00,jm1,jyy,jxx,jKK,d,v"))] "TARGET_VX" "@ vlr\t%v0,%v1 @@ -178,8 +178,8 @@ ; However, this would probably be slower. (define_insn "mov" - [(set (match_operand:V_8 0 "nonimmediate_operand" "=v,v,d, v,QR, v, v, v, v,d, Q, S, Q, S, d, d,d,d,d,R,T") - (match_operand:V_8 1 "general_operand" " v,d,v,QR, v,j00,jm1,jyy,jxx,d,j00,j00,jm1,jm1,j00,jm1,R,T,b,d,d"))] + [(set (match_operand:V_8 0 "nonimmediate_operand" "=v,v,d,v,R, v, v, v, v,d, Q, S, Q, S, d, d,d,d,d,R,T") + (match_operand:V_8 1 "general_operand" " v,d,v,R,v,j00,jm1,jyy,jxx,d,j00,j00,jm1,jm1,j00,jm1,R,T,b,d,d"))] "" "@ vlr\t%v0,%v1 @@ -206,8 +206,8 @@ [(set_attr "op_type" "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SI,SIY,SI,SIY,RI,RI,RX,RXY,RIL,RX,RXY")]) (define_insn "mov" - [(set (match_operand:V_16 0 "nonimmediate_operand" "=v,v,d, v,QR, v, v, v, v,d, Q, Q, d, d,d,d,d,R,T,b") - (match_operand:V_16 1 "general_operand" " v,d,v,QR, v,j00,jm1,jyy,jxx,d,j00,jm1,j00,jm1,R,T,b,d,d,d"))] + [(set (match_operand:V_16 0 "nonimmediate_operand" "=v,v,d,v,R, v, v, v, v,d, Q, Q, d, d,d,d,d,R,T,b") + (match_operand:V_16 1 "general_operand" " v,d,v,R,v,j00,jm1,jyy,jxx,d,j00,jm1,j00,jm1,R,T,b,d,d,d"))] "" "@ vlr\t%v0,%v1 @@ -233,8 +233,8 @@ [(set_attr "op_type" "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SIL,SIL,RI,RI,RX,RXY,RIL,RX,RXY,RIL")]) (define_insn "mov" - [(set (match_operand:V_32 0 "nonimmediate_operand" "=f,f,f,R,T,v,v,d, v,QR, f, v, v, v, v, Q, Q, d, d,d,d,d,d,R,T,b") - (match_operand:V_32 1 "general_operand" " f,R,T,f,f,v,d,v,QR, v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,b,d,R,T,d,d,d"))] + [(set (match_operand:V_32 0 "nonimmediate_operand" "=f,f,f,R,T,v,v,d,v,R, f, v, v, v, v, Q, Q, d, d,d,d,d,d,R,T,b") + (match_operand:V_32 1 "general_operand" " f,R,T,f,f,v,d,v,R,v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,b,d,R,T,d,d,d"))] "TARGET_VX" "@ lder\t%v0,%v1 @@ -268,9 +268,9 @@ (define_insn "mov" [(set (match_operand:V_64 0 "nonimmediate_operand" - "=f,f,f,R,T,v,v,d, v,QR, f, v, v, v, v, Q, Q, d, d,f,d,d,d, d,RT,b") + "=f,f,f,R,T,v,v,d,v,R, f, v, v, v, v, Q, Q, d, d,f,d,d,d,d,T,b") (match_operand:V_64 1 "general_operand" - " f,R,T,f,f,v,d,v,QR, v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,d,f,b,d,RT, d,d"))] + " f,R,T,f,f,v,d,v,R,v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,d,f,b,d,T,d,d"))] "TARGET_ZARCH" "@ ldr\t%0,%1 @@ -322,10 +322,10 @@ ; up with vl vlvgg vst. Shouldn't the middle-end be able to handle ; that itself? (define_insn "*vec_set" - [(set (match_operand:V 0 "register_operand" "=v, v,v") - (unspec:V [(match_operand: 1 "general_operand" "d,QR,K") - (match_operand:SI 2 "nonmemory_operand" "an, I,I") - (match_operand:V 3 "register_operand" "0, 0,0")] + [(set (match_operand:V 0 "register_operand" "=v,v,v") + (unspec:V [(match_operand: 1 "general_operand" "d,R,K") + (match_operand:SI 2 "nonmemory_operand" "an,I,I") + (match_operand:V 3 "register_operand" "0,0,0")] UNSPEC_VEC_SET))] "TARGET_VX && (!CONST_INT_P (operands[2]) @@ -359,9 +359,9 @@ "TARGET_VX") (define_insn "*vec_extract" - [(set (match_operand: 0 "nonimmediate_operand" "=d,QR") - (unspec: [(match_operand:V 1 "register_operand" "v, v") - (match_operand:SI 2 "nonmemory_operand" "an, I")] + [(set (match_operand: 0 "nonimmediate_operand" "=d,R") + (unspec: [(match_operand:V 1 "register_operand" "v,v") + (match_operand:SI 2 "nonmemory_operand" "an,I")] UNSPEC_VEC_EXTRACT))] "TARGET_VX && (!CONST_INT_P (operands[2]) @@ -404,7 +404,7 @@ (define_insn "*vec_splats" [(set (match_operand:V_HW 0 "register_operand" "=v,v,v,v") - (vec_duplicate:V_HW (match_operand: 1 "general_operand" "QR,K,v,d")))] + (vec_duplicate:V_HW (match_operand: 1 "general_operand" " R,K,v,d")))] "TARGET_VX" "@ vlrep\t%v0,%1 diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index c4a837b..9ab429e 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -70,7 +70,7 @@ [(set (match_operand:V_HW_32_64 0 "register_operand" "=v") (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0") (match_operand: 2 "register_operand" "v") - (match_operand:BLK 3 "memory_operand" "QR") + (match_operand:BLK 3 "memory_operand" "R") (match_operand:QI 4 "const_mask_operand" "C")] UNSPEC_VEC_GATHER))] "TARGET_VX && UINTVAL (operands[4]) < GET_MODE_NUNITS (mode)" @@ -170,7 +170,7 @@ (define_insn "vec_insert_and_zero" [(set (match_operand:V_HW 0 "register_operand" "=v") - (unspec:V_HW [(match_operand: 1 "memory_operand" "QR")] + (unspec:V_HW [(match_operand: 1 "memory_operand" "R")] UNSPEC_VEC_INSERT_AND_ZERO))] "TARGET_VX" "vllez\t%v0,%1" @@ -178,7 +178,7 @@ (define_insn "vlbb" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "QR") + (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "R") (match_operand:QI 2 "const_mask_operand" "C")] UNSPEC_VEC_LOAD_BNDRY))] "TARGET_VX && UINTVAL (operands[2]) < 7"