From patchwork Thu Apr 28 17:10:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 616344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qwk0V4dLbz9t7P for ; Fri, 29 Apr 2016 03:12:25 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=KMVRyoKi; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=cueE80Hw8O+6bHdE 4UxsZ2WVz33RLu0SYHnjd9+3FiNt3nD3ViHIZF7cOntbyQEfQJ/KBTnHPG4MeX36 OCg3KVF+2fURIpW2X00JGunw0L+UEy4N5tHTkdtph4n/5+RbF8DZDiND2QV8LSC0 qUUl3zKKii+3Q47PwLqvbMfEs3Q= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=hbUYi9Igf9/Ek0ZQVd1Ivh 6UwR0=; b=KMVRyoKiB4VT1u/b1cBm1J/PgYlCUc9zasp4FSuozTYEkM2/yvJxsr eHkp/fYPhVWijfVgV/XMsVBGxabM2wg8FfLb5zcnc8YCsq0v5OGlac1HZFSW7v44 BjQ6A8fkJcRry6ecOtmdm+6ocZIIyj39C5kTuozRLjXvTJZKM4xsQ= Received: (qmail 60229 invoked by alias); 28 Apr 2016 17:12:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60210 invoked by uid 89); 28 Apr 2016 17:12:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: smtprelay.synopsys.com Received: from smtprelay4.synopsys.com (HELO smtprelay.synopsys.com) (198.182.47.9) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Thu, 28 Apr 2016 17:12:07 +0000 Received: from dc8secmta1.synopsys.com (dc8secmta1.synopsys.com [10.13.218.200]) by smtprelay.synopsys.com (Postfix) with ESMTP id E438E24E068E; Thu, 28 Apr 2016 10:12:03 -0700 (PDT) Received: from dc8secmta1.internal.synopsys.com (dc8secmta1.internal.synopsys.com [127.0.0.1]) by dc8secmta1.internal.synopsys.com (Service) with ESMTP id C5B1C27113; Thu, 28 Apr 2016 10:12:03 -0700 (PDT) Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by dc8secmta1.internal.synopsys.com (Service) with ESMTP id 958E827102; Thu, 28 Apr 2016 10:12:03 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 7CCB18DA; Thu, 28 Apr 2016 10:12:03 -0700 (PDT) Received: from US01WEHTC3.internal.synopsys.com (us01wehtc3.internal.synopsys.com [10.15.84.232]) by mailhost.synopsys.com (Postfix) with ESMTP id 45A138D6; Thu, 28 Apr 2016 10:12:03 -0700 (PDT) Received: from IN01WEHTCB.internal.synopsys.com (10.144.199.106) by US01WEHTC3.internal.synopsys.com (10.15.84.232) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 28 Apr 2016 10:12:02 -0700 Received: from IN01WEHTCA.internal.synopsys.com (10.144.199.103) by IN01WEHTCB.internal.synopsys.com (10.144.199.105) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 28 Apr 2016 22:42:00 +0530 Received: from nl20droid1.internal.synopsys.com (10.100.24.228) by IN01WEHTCA.internal.synopsys.com (10.144.199.243) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 28 Apr 2016 22:42:00 +0530 From: Claudiu Zissulescu To: CC: , , , Subject: [PATCH] [ARC] Fix unwanted match for sign extend 16-bit constant. Date: Thu, 28 Apr 2016 19:10:30 +0200 Message-ID: <1461863430-22916-1-git-send-email-claziss@synopsys.com> In-Reply-To: <5721F84D.2090002@amylaar.uk> References: <5721F84D.2090002@amylaar.uk> MIME-Version: 1.0 Please find the updated patch. Claudiu gcc/ 2016-04-28 Claudiu Zissulescu * config/arc/arc.h (UNSIGNED_INT12, UNSIGNED_INT16): Define. * config/arc/arc.md (umulhisi3): Use arc_short_operand predicate. (umulhisi3_imm): Update predicates and constraint letters. (umulhisi3_reg): Declare instruction as commutative. * config/arc/constraints.md (U12, U16): New constraints. * config/arc/predicates.md (short_unsigned_const_operand): New predicate. (arc_short_operand): Likewise. * testsuite/gcc.target/arc/umulsihi3_z.c: New file. --- gcc/config/arc/arc.h | 2 ++ gcc/config/arc/arc.md | 14 +++++++------- gcc/config/arc/constraints.md | 11 +++++++++++ gcc/config/arc/predicates.md | 8 ++++++++ gcc/testsuite/gcc.target/arc/umulsihi3_z.c | 23 +++++++++++++++++++++++ 5 files changed, 51 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/umulsihi3_z.c diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index 37c1afa..1b75099 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -795,6 +795,8 @@ extern enum reg_class arc_regno_reg_class[]; #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40) #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80) #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100) +#define UNSIGNED_INT12(X) ((unsigned) (X) < 0x800) +#define UNSIGNED_INT16(X) ((unsigned) (X) < 0x10000) #define IS_ONE(X) ((X) == 1) #define IS_ZERO(X) ((X) == 0) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 8ec0ce0..e0f74e4 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1720,21 +1720,21 @@ (define_expand "umulhisi3" [(set (match_operand:SI 0 "register_operand" "") (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "")) - (zero_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))] + (zero_extend:SI (match_operand:HI 2 "arc_short_operand" ""))))] "TARGET_MPYW" "{ if (CONSTANT_P (operands[2])) { - emit_insn (gen_umulhisi3_imm (operands[0], operands[1], operands[2])); - DONE; + emit_insn (gen_umulhisi3_imm (operands[0], operands[1], operands[2])); + DONE; } }" ) (define_insn "umulhisi3_imm" - [(set (match_operand:SI 0 "register_operand" "=r, r,r, r, r") - (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" " 0, r,0, 0, r")) - (match_operand:HI 2 "short_const_int_operand" " L, L,I,C16,C16")))] + [(set (match_operand:SI 0 "register_operand" "=r, r, r, r, r") + (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0, r, 0, 0, r")) + (match_operand:HI 2 "short_unsigned_const_operand" " L, L,U12,U16,U16")))] "TARGET_MPYW" "mpyuw%? %0,%1,%2" [(set_attr "length" "4,4,4,8,8") @@ -1746,7 +1746,7 @@ (define_insn "umulhisi3_reg" [(set (match_operand:SI 0 "register_operand" "=Rcqq, r, r") - (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" " 0, 0, r")) + (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" " %0, 0, r")) (zero_extend:SI (match_operand:HI 2 "register_operand" " Rcqq, r, r"))))] "TARGET_MPYW" "mpyuw%? %0,%1,%2" diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index 668b60a..cdf94ef 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -427,3 +427,14 @@ "A memory with only a base register" (match_operand 0 "mem_noofs_operand")) +(define_constraint "U12" + "@internal + An unsigned 12-bit integer constant." + (and (match_code "const_int") + (match_test "UNSIGNED_INT12 (ival)"))) + +(define_constraint "U16" + "@internal + An unsigned 16-bit integer constant" + (and (match_code "const_int") + (match_test "UNSIGNED_INT16 (ival)"))) diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md index 3c657c6..9542b22 100644 --- a/gcc/config/arc/predicates.md +++ b/gcc/config/arc/predicates.md @@ -819,3 +819,11 @@ (define_predicate "double_register_operand" (ior (match_test "even_register_operand (op, mode)") (match_test "arc_double_register_operand (op, mode)"))) + +(define_predicate "short_unsigned_const_operand" + (and (match_code "const_int") + (match_test "satisfies_constraint_U16 (op)"))) + +(define_predicate "arc_short_operand" + (ior (match_test "register_operand (op, mode)") + (match_test "short_unsigned_const_operand (op, mode)"))) diff --git a/gcc/testsuite/gcc.target/arc/umulsihi3_z.c b/gcc/testsuite/gcc.target/arc/umulsihi3_z.c new file mode 100644 index 0000000..cf1c00d --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/umulsihi3_z.c @@ -0,0 +1,23 @@ +/* Check if the optimizers are not removing the umulsihi3_imm + instruction. */ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-inline" } */ + +#include + +static int32_t test (int16_t reg_val) +{ + int32_t x = (reg_val & 0xf) * 62500; + return x; +} + +int main (void) +{ + volatile int32_t x = 0xc172; + x = test (x); + + if (x != 0x0001e848) + __builtin_abort (); + return 0; +} +