From patchwork Mon Apr 18 14:33:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 611757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qpW0s489kz9t3V for ; Tue, 19 Apr 2016 00:36:13 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=amJyksFV; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=ZZ+3HWJWC2j6JeHY nI8GwQOMiVXdMbEiHZlx49K4QOeKDmd82W2BbFBuXJL0C47GzCDuQoVyjDrwEqEr kMAdMvKHwCi2U+ty0rsCBAbp/lWCUaf+kWV3jhxLZTQf+LrBPMUHmJD1nIC2BvLZ Jx98+U0Pxe9rarpmPX5lXq/2LJI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=XlI3Rceen1GoQV6BnEodlb hAC5o=; b=amJyksFV8Tm9jzMqd/AsnXvMzjMVEt7v4XFsqPRVrgVDtQRms4xtIl nN64Z8AmAvdE4cEsrT5iMe3aYhDqe1gWsaJG81u3SIkFjCvBKZmtoSW2j9FYQE9X yEjuMzl/4Q2TBkt1XKS+LqSiERPEwtlnhY3mN4MlPhXZRbZQF76kE= Received: (qmail 46929 invoked by alias); 18 Apr 2016 14:35:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 46836 invoked by uid 89); 18 Apr 2016 14:35:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=H*RU:sk:smtprel, Hx-spam-relays-external:sk:smtprel, HX-HELO:sk:smtprel, FPX X-HELO: smtprelay.synopsys.com Received: from us01smtprelay-2.synopsys.com (HELO smtprelay.synopsys.com) (198.182.47.9) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 18 Apr 2016 14:35:19 +0000 Received: from dc8secmta2.synopsys.com (dc8secmta2.synopsys.com [10.13.218.202]) by smtprelay.synopsys.com (Postfix) with ESMTP id 596A424E1F58; Mon, 18 Apr 2016 07:35:18 -0700 (PDT) Received: from dc8secmta2.internal.synopsys.com (dc8secmta2.internal.synopsys.com [127.0.0.1]) by dc8secmta2.internal.synopsys.com (Service) with ESMTP id 4DB1BA4112; Mon, 18 Apr 2016 07:35:18 -0700 (PDT) Received: from mailhost.synopsys.com (unknown [10.13.184.66]) by dc8secmta2.internal.synopsys.com (Service) with ESMTP id 17354A4102; Mon, 18 Apr 2016 07:35:18 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 05B5C1AB; Mon, 18 Apr 2016 07:35:18 -0700 (PDT) Received: from US01WEHTC2.internal.synopsys.com (us01wehtc2.internal.synopsys.com [10.12.239.237]) by mailhost.synopsys.com (Postfix) with ESMTP id F03BC1AA; Mon, 18 Apr 2016 07:35:17 -0700 (PDT) Received: from IN01WEHTCB.internal.synopsys.com (10.144.199.106) by US01WEHTC2.internal.synopsys.com (10.12.239.237) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 18 Apr 2016 07:35:17 -0700 Received: from IN01WEHTCA.internal.synopsys.com (10.144.199.103) by IN01WEHTCB.internal.synopsys.com (10.144.199.105) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 18 Apr 2016 20:05:14 +0530 Received: from nl20droid1.internal.synopsys.com (10.100.24.228) by IN01WEHTCA.internal.synopsys.com (10.144.199.243) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 18 Apr 2016 20:05:14 +0530 From: Claudiu Zissulescu To: CC: , , , Subject: [PATCH 2/6] [ARC] Fix FPX/FPUDA code gen when compiling for big-endian. Date: Mon, 18 Apr 2016 16:33:44 +0200 Message-ID: <1460990028-5718-3-git-send-email-claziss@synopsys.com> In-Reply-To: <1460990028-5718-1-git-send-email-claziss@synopsys.com> References: <1460990028-5718-1-git-send-email-claziss@synopsys.com> MIME-Version: 1.0 OK to apply? Claudiu gcc/ 2016-04-18 Claudiu Zissulescu * config/arc/arc.c (arc_process_double_reg_moves): Fix for big-endian compilation. * config/arc/arc.md (addf3): Likewise. (subdf3): Likewise. (muldf3): Likewise. --- gcc/config/arc/arc.c | 12 ++++++++---- gcc/config/arc/arc.md | 18 +++++++++--------- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index d60db50..f4bef3e 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -8647,8 +8647,10 @@ arc_process_double_reg_moves (rtx *operands) { /* When we have 'mov D, r' or 'mov D, D' then get the target register pair for use with LR insn. */ - rtx destHigh = simplify_gen_subreg(SImode, dest, DFmode, 4); - rtx destLow = simplify_gen_subreg(SImode, dest, DFmode, 0); + rtx destHigh = simplify_gen_subreg (SImode, dest, DFmode, + TARGET_BIG_ENDIAN ? 0 : 4); + rtx destLow = simplify_gen_subreg (SImode, dest, DFmode, + TARGET_BIG_ENDIAN ? 4 : 0); /* Produce the two LR insns to get the high and low parts. */ emit_insn (gen_rtx_SET (destHigh, @@ -8665,8 +8667,10 @@ arc_process_double_reg_moves (rtx *operands) { /* When we have 'mov r, D' or 'mov D, D' and we have access to the LR insn get the target register pair. */ - rtx srcHigh = simplify_gen_subreg(SImode, src, DFmode, 4); - rtx srcLow = simplify_gen_subreg(SImode, src, DFmode, 0); + rtx srcHigh = simplify_gen_subreg (SImode, src, DFmode, + TARGET_BIG_ENDIAN ? 0 : 4); + rtx srcLow = simplify_gen_subreg (SImode, src, DFmode, + TARGET_BIG_ENDIAN ? 4 : 0); emit_insn (gen_rtx_UNSPEC_VOLATILE (Pmode, gen_rtvec (3, dest, srcHigh, srcLow), diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 9766547..74530b1 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -5681,9 +5681,9 @@ { if (GET_CODE (operands[2]) == CONST_DOUBLE) { - rtx high, low, tmp; - split_double (operands[2], &low, &high); - tmp = force_reg (SImode, high); + rtx first, second, tmp; + split_double (operands[2], &first, &second); + tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second); emit_insn (gen_adddf3_insn (operands[0], operands[1], operands[2], tmp, const0_rtx)); } @@ -5718,10 +5718,10 @@ if ((GET_CODE (operands[1]) == CONST_DOUBLE) || GET_CODE (operands[2]) == CONST_DOUBLE) { - rtx high, low, tmp; + rtx first, second, tmp; int const_index = ((GET_CODE (operands[1]) == CONST_DOUBLE) ? 1 : 2); - split_double (operands[const_index], &low, &high); - tmp = force_reg (SImode, high); + split_double (operands[const_index], &first, &second); + tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second); emit_insn (gen_subdf3_insn (operands[0], operands[1], operands[2], tmp, const0_rtx)); } @@ -5753,9 +5753,9 @@ { if (GET_CODE (operands[2]) == CONST_DOUBLE) { - rtx high, low, tmp; - split_double (operands[2], &low, &high); - tmp = force_reg (SImode, high); + rtx first, second, tmp; + split_double (operands[2], &first, &second); + tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second); emit_insn (gen_muldf3_insn (operands[0], operands[1], operands[2], tmp, const0_rtx)); }