From patchwork Thu Jan 14 16:33:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 567679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FFBD14031E for ; Fri, 15 Jan 2016 07:44:26 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=XSBCFCeq; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=p4zgu7Y58/dRy2YyZDn/fiEYtDCzTuRJWFBtjHzkuZUVRCNAS2iJx HllBl09HBmkla+iVyiQ4kgKJHQXFM7kKQAhYwVK/k01ioYAkKO4beRxm1riWUMHf LzpINqnkumKyXYWTjs1oXQ3C7MX/P0oOnjHArfVztjU7cI8AgvuWd0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; s=default; bh=wxrb1x9dCA5sOv4D8YsmJ6DG2FE=; b=XSBCFCeqJIS90HcjevDtry4iTqyi IAwRnotJxBcLqJEOlX0pRCYw/2Q9KEk6NvHojsROb2Hxs8m3cUPeCb96Tprqd8Au jvWRu+ThMvoQh17ot3vD7QdYO1utxjIcXTE23E4wYdyF56pHcqXXtUo5NiOQFA+j P8wH3ZVABM80O6M= Received: (qmail 121729 invoked by alias); 14 Jan 2016 20:44:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 121718 invoked by uid 89); 14 Jan 2016 20:44:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.7 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=variants, krebbel@linux.vnet.ibm.com, U*krebbel, krebbellinuxvnetibmcom X-HELO: e06smtp11.uk.ibm.com Received: from e06smtp11.uk.ibm.com (HELO e06smtp11.uk.ibm.com) (195.75.94.107) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Thu, 14 Jan 2016 20:44:16 +0000 Received: from localhost by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Date: Thu, 14 Jan 2016 17:33:33 +0100 Message-Id: <1452789254-12603-9-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1452789254-12603-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1452789254-12603-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16011420-0041-0000-0000-0000072C6D01 X-IsSubscribed: yes While trying to get rid of the Y constraint in the setmem patterns I noticed that for these patterns it isn't even a problem since these always only use the constraint with a Pmode match_operand. But while being at it I've tried to fold some of the patterns a bit. gcc/ChangeLog: 2016-01-14 Andreas Krebbel * config/s390/predicates.md ("const_int_8bitset_operand"): New predicate. * config/s390/s390.md ("*setmem_long", "*setmem_long_and") ("*setmem_long_31z", "*setmem_long_and_31z"): Merge into ... ("*setmem_long"): New pattern definition. * config/s390/subst.md ("setmem_31z_subst", "setmem_and_subst"): New substitution rules with the required attributes. --- gcc/config/s390/predicates.md | 6 +++++ gcc/config/s390/s390.md | 60 +++++-------------------------------------- gcc/config/s390/subst.md | 52 +++++++++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 53 deletions(-) diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md index b58cb22..bc25773 100644 --- a/gcc/config/s390/predicates.md +++ b/gcc/config/s390/predicates.md @@ -140,6 +140,12 @@ (define_predicate "const_int_6bitset_operand" (and (match_code "const_int") (match_test "(INTVAL (op) & 63) == 63"))) + +; An integer operand with the lowest order 8 bit all ones. +(define_predicate "const_int_8bitset_operand" + (and (match_code "const_int") + (match_test "(INTVAL (op) & 255) == 255"))) + (define_predicate "nonzero_shift_count_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)"))) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 389b523..350ed36 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3313,62 +3313,16 @@ ; Patterns for 31 bit + Esa and 64 bit + Zarch. -(define_insn "*setmem_long" +(define_insn "*setmem_long" [(clobber (match_operand: 0 "register_operand" "=d")) - (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0)) - (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y") - (subreg:P (match_dup 3) )] + (set (mem:BLK (subreg:P (match_operand: 1 "register_operand" "0") 0)) + (unspec:BLK [(match_operand:P 3 "shift_count_or_setmem_operand" "Y") + (subreg:P (match_operand: 2 "register_operand" "0") )] UNSPEC_REPLICATE_BYTE)) - (use (match_operand: 1 "register_operand" "d")) + (use (match_operand: 4 "register_operand" "d")) (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT || !TARGET_ZARCH" - "mvcle\t%0,%1,%Y2\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -(define_insn "*setmem_long_and" - [(clobber (match_operand: 0 "register_operand" "=d")) - (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0)) - (unspec:BLK [(and:P - (match_operand:P 2 "shift_count_or_setmem_operand" "Y") - (match_operand:P 4 "const_int_operand" "n")) - (subreg:P (match_dup 3) )] - UNSPEC_REPLICATE_BYTE)) - (use (match_operand: 1 "register_operand" "d")) - (clobber (reg:CC CC_REGNUM))] - "(TARGET_64BIT || !TARGET_ZARCH) && - (INTVAL (operands[4]) & 255) == 255" - "mvcle\t%0,%1,%Y2\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets -; of the SImode subregs. - -(define_insn "*setmem_long_31z" - [(clobber (match_operand:TI 0 "register_operand" "=d")) - (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) - (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) - (use (match_operand:TI 1 "register_operand" "d")) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT && TARGET_ZARCH" - "mvcle\t%0,%1,%Y2\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -(define_insn "*setmem_long_and_31z" - [(clobber (match_operand:TI 0 "register_operand" "=d")) - (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) - (unspec:BLK [(and:SI - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 4 "const_int_operand" "n")) - (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) - (use (match_operand:TI 1 "register_operand" "d")) - (clobber (reg:CC CC_REGNUM))] - "(!TARGET_64BIT && TARGET_ZARCH) && - (INTVAL (operands[4]) & 255) == 255" - "mvcle\t%0,%1,%Y2\;jo\t.-4" + "" + "mvcle\t%0,%4,%Y3\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md index ccff40e..a633f3f 100644 --- a/gcc/config/s390/subst.md +++ b/gcc/config/s390/subst.md @@ -126,3 +126,55 @@ (clobber (match_scratch:DSI 0 "=d,d,d,d"))]) (define_subst_attr "cconly" "cconly_subst" "" "_cconly") + + +;; setmem substitution patterns + + +; Turn the DImode in the 31 bit pattern into TImode to enforce +; register pair usage even with -mzarch. +; The subreg offset is adjusted accordingly. +(define_subst "setmem_31z_subst" + [(clobber (match_operand:DI 0 "register_operand" "")) + (set (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "") 0)) + (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "") + (subreg:SI (match_operand:DI 4 "register_operand" "") + 0)] + UNSPEC_REPLICATE_BYTE)) + (use (match_operand:DI 1 "register_operand" "")) + (clobber (reg:CC CC_REGNUM))] +"" + [(clobber (match_operand:TI 0 "register_operand" "")) + (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "") 4)) + (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "") + (subreg:SI (match_operand:TI 4 "register_operand" "") + 12)] + UNSPEC_REPLICATE_BYTE)) + (use (match_operand:TI 1 "register_operand" "")) + (clobber (reg:CC CC_REGNUM))]) + +(define_subst_attr "setmem_31z" "setmem_31z_subst" "" "_31z") +(define_subst_attr "setmem_31z_cond" "setmem_31z_subst" "TARGET_64BIT || !TARGET_ZARCH" + "!TARGET_64BIT && TARGET_ZARCH") + +; Add an AND operation on the padding byte operand. Only the lowest 8 +; bit are used and the rest is ignored. +(define_subst "setmem_and_subst" + [(clobber (match_operand:TDI 0 "register_operand" "")) + (set (mem:BLK (subreg:DSI (match_operand:TDI 1 "register_operand" "") 0)) + (unspec:BLK [(match_operand:DSI 2 "shift_count_or_setmem_operand" "") + (match_operand:DSI 3 "register_operand" "")] + UNSPEC_REPLICATE_BYTE)) + (use (match_operand:TDI 4 "register_operand" "")) + (clobber (reg:CC CC_REGNUM))] +"" + [(clobber (match_dup 0)) + (set (mem:BLK (subreg:SI (match_dup 1) 0)) + (unspec:BLK [(and:DSI (match_dup 2) + (match_operand:DSI 5 "const_int_8bitset_operand" "")) + (match_dup 3)] + UNSPEC_REPLICATE_BYTE)) + (use (match_dup 4)) + (clobber (reg:CC CC_REGNUM))]) + +(define_subst_attr "setmem_and" "setmem_and_subst" "" "_and")