From patchwork Tue Nov 3 14:27:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 539444 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8CA491402D6 for ; Wed, 4 Nov 2015 01:28:34 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=D2RXQBEA; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type :content-transfer-encoding; q=dns; s=default; b=N7j8Yr0n4ix1xLAn b/Q6WKKwhAzfHQOKeY7kVCorYNNBcMG0FY96IXdSscitPmZamZ9dXdhgy5+JPLGJ 0UJHtDUispXwOLxbYk6vTK9VBfBhDeSeCJXhEoXAW6/5lJS2J+sx7PQI2v+uhX+1 z0Bbb8G7FlkFarTwycRMoGEWL4Q= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type :content-transfer-encoding; s=default; bh=gPmbRyeMmXeI07PJRVoghv snGPs=; b=D2RXQBEA3EDyTKWsX5xTd/oVRCdEoH+Ywan8Zmg/PCUxsKL/QT/Oyk kU2qqxsBKvOSd4E91KKtyD1P/ptUavsDjIimR13C1Wq+nKClca0rHViHKN+weU+M F39fhqZ+kRjw27GHqaI71mNPpx0HlHcrwNZ1zDdPvqy91S/+NZcLg= Received: (qmail 44994 invoked by alias); 3 Nov 2015 14:27:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 44947 invoked by uid 89); 3 Nov 2015 14:27:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Nov 2015 14:27:54 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-21-dh4i_DanSUiFdi6MXwjbYw-1; Tue, 03 Nov 2015 14:27:47 +0000 Received: from arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Nov 2015 14:27:47 +0000 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Subject: [PATCH][i386]Migrate reduction optabs to reduc__scal Date: Tue, 3 Nov 2015 14:27:41 +0000 Message-Id: <1446560861-31206-1-git-send-email-alan.lawrence@arm.com> X-MC-Unique: dh4i_DanSUiFdi6MXwjbYw-1 X-IsSubscribed: yes This migrates the various reduction optabs in sse.md to use the reduce-to-scalar form. I took the straightforward approach (equivalent to the migration code in expr.c/optabs.c) of generating a vector temporary, using the existing code to reduce to that, and extracting lane 0, in each pattern. Bootstrapped + check-gcc + check-g++. Ok for trunk? gcc/ChangeLog: * config/i386/sse.md (reduc_splus_v8df): Rename to... (reduc_plus_scal_v8df): ...here; reduce to temp and extract scalar. (reduc_splus_v4df): Rename to... (reduc_plus_scal_v4df): ...here; reduce to temp and extract scalar. (reduc_splus_v2df): Rename to... (reduc_plus_scal_v2df): ...here; reduce to temp and extract scalar. (reduc_splus_v16sf): Rename to... (reduc_plus_scal_v16sf): ...here; reduce to temp and extract scalar. (reduc_splus_v8sf): Rename to... (reduc_plus_scal_v8sf): ...here; reduce to temp and extract scalar. (reduc_splus_v4sf): Rename to... (reduc_plus_scal_v4sf): ...here; reduce to temp and extract scalar. (reduc__, all 3 variants): Rename each to... (reduc__scal_): ...here; reduce to temp and extract scalar. (reduc_umin_v8hf): Rename to... (reduc_umin_scal_v8hf): ...here; reduce to temp and extract scalar. --- gcc/config/i386/sse.md | 82 +++++++++++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 31 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 43dcc6a..041e514 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2424,73 +2424,85 @@ (set_attr "prefix_rep" "1,*") (set_attr "mode" "V4SF")]) -(define_expand "reduc_splus_v8df" - [(match_operand:V8DF 0 "register_operand") +(define_expand "reduc_plus_scal_v8df" + [(match_operand:DF 0 "register_operand") (match_operand:V8DF 1 "register_operand")] "TARGET_AVX512F" { - ix86_expand_reduc (gen_addv8df3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (V8DFmode); + ix86_expand_reduc (gen_addv8df3, tmp, operands[1]); + emit_insn (gen_vec_extractv8df (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v4df" - [(match_operand:V4DF 0 "register_operand") +(define_expand "reduc_plus_scal_v4df" + [(match_operand:DF 0 "register_operand") (match_operand:V4DF 1 "register_operand")] "TARGET_AVX" { rtx tmp = gen_reg_rtx (V4DFmode); rtx tmp2 = gen_reg_rtx (V4DFmode); + rtx vec_res = gen_reg_rtx (V4DFmode); emit_insn (gen_avx_haddv4df3 (tmp, operands[1], operands[1])); emit_insn (gen_avx_vperm2f128v4df3 (tmp2, tmp, tmp, GEN_INT (1))); - emit_insn (gen_addv4df3 (operands[0], tmp, tmp2)); + emit_insn (gen_addv4df3 (vec_res, tmp, tmp2)); + emit_insn (gen_vec_extractv4df (operands[0], vec_res, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v2df" - [(match_operand:V2DF 0 "register_operand") +(define_expand "reduc_plus_scal_v2df" + [(match_operand:DF 0 "register_operand") (match_operand:V2DF 1 "register_operand")] "TARGET_SSE3" { - emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1])); + rtx tmp = gen_reg_rtx (V2DFmode); + emit_insn (gen_sse3_haddv2df3 (tmp, operands[1], operands[1])); + emit_insn (gen_vec_extractv2df (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v16sf" - [(match_operand:V16SF 0 "register_operand") +(define_expand "reduc_plus_scal_v16sf" + [(match_operand:SF 0 "register_operand") (match_operand:V16SF 1 "register_operand")] "TARGET_AVX512F" { - ix86_expand_reduc (gen_addv16sf3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (V16SFmode); + ix86_expand_reduc (gen_addv16sf3, tmp, operands[1]); + emit_insn (gen_vec_extractv16sf (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v8sf" - [(match_operand:V8SF 0 "register_operand") +(define_expand "reduc_plus_scal_v8sf" + [(match_operand:SF 0 "register_operand") (match_operand:V8SF 1 "register_operand")] "TARGET_AVX" { rtx tmp = gen_reg_rtx (V8SFmode); rtx tmp2 = gen_reg_rtx (V8SFmode); + rtx vec_res = gen_reg_rtx (V8SFmode); emit_insn (gen_avx_haddv8sf3 (tmp, operands[1], operands[1])); emit_insn (gen_avx_haddv8sf3 (tmp2, tmp, tmp)); emit_insn (gen_avx_vperm2f128v8sf3 (tmp, tmp2, tmp2, GEN_INT (1))); - emit_insn (gen_addv8sf3 (operands[0], tmp, tmp2)); + emit_insn (gen_addv8sf3 (vec_res, tmp, tmp2)); + emit_insn (gen_vec_extractv8sf (operands[0], vec_res, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v4sf" - [(match_operand:V4SF 0 "register_operand") +(define_expand "reduc_plus_scal_v4sf" + [(match_operand:SF 0 "register_operand") (match_operand:V4SF 1 "register_operand")] "TARGET_SSE" { + rtx vec_res = gen_reg_rtx (V4SFmode); if (TARGET_SSE3) { rtx tmp = gen_reg_rtx (V4SFmode); emit_insn (gen_sse3_haddv4sf3 (tmp, operands[1], operands[1])); - emit_insn (gen_sse3_haddv4sf3 (operands[0], tmp, tmp)); + emit_insn (gen_sse3_haddv4sf3 (vec_res, tmp, tmp)); } else - ix86_expand_reduc (gen_addv4sf3, operands[0], operands[1]); + ix86_expand_reduc (gen_addv4sf3, vec_res, operands[1]); + emit_insn (gen_vec_extractv4sf (operands[0], vec_res, const0_rtx)); DONE; }) @@ -2504,43 +2516,51 @@ (V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F")]) -(define_expand "reduc__" +(define_expand "reduc__scal_" [(smaxmin:REDUC_SMINMAX_MODE - (match_operand:REDUC_SMINMAX_MODE 0 "register_operand") + (match_operand: 0 "register_operand") (match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))] "" { - ix86_expand_reduc (gen_3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (mode); + ix86_expand_reduc (gen_3, tmp, operands[1]); + emit_insn (gen_vec_extract (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc__" +(define_expand "reduc__scal_" [(umaxmin:VI_AVX512BW - (match_operand:VI_AVX512BW 0 "register_operand") + (match_operand: 0 "register_operand") (match_operand:VI_AVX512BW 1 "register_operand"))] "TARGET_AVX512F" { - ix86_expand_reduc (gen_3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (mode); + ix86_expand_reduc (gen_3, tmp, operands[1]); + emit_insn (gen_vec_extract (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc__" +(define_expand "reduc__scal_" [(umaxmin:VI_256 - (match_operand:VI_256 0 "register_operand") + (match_operand: 0 "register_operand") (match_operand:VI_256 1 "register_operand"))] "TARGET_AVX2" { - ix86_expand_reduc (gen_3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (mode); + ix86_expand_reduc (gen_3, tmp, operands[1]); + emit_insn (gen_vec_extract (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc_umin_v8hi" +(define_expand "reduc_umin_scal_v8hi" [(umin:V8HI - (match_operand:V8HI 0 "register_operand") + (match_operand:HI 0 "register_operand") (match_operand:V8HI 1 "register_operand"))] "TARGET_SSE4_1" { - ix86_expand_reduc (gen_uminv8hi3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (V8HImode); + ix86_expand_reduc (gen_uminv8hi3, tmp, operands[1]); + emit_insn (gen_vec_extractv8hi (operands[0], tmp, const0_rtx)); DONE; })