From patchwork Tue Sep 15 09:14:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 517755 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C9C261402C4 for ; Tue, 15 Sep 2015 19:17:18 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=MTuyEUOp; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; q=dns; s=default; b=OWl TladPrir6q4M72JUOdkKd+YEkxtd5ro9Jyca2Kizy4KTCmy8Q9vTopqVv9DQXJPy M8sYmZcbUnOAXQJkzRAUqNu1QFHcMOM0uQXHnWxybL22OPwgWxM+CcaS1b5Ba//p mhLvWmtaxkIDTT01Nyd9TEHFcGrYWoCqQhQN4c8M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; s=default; bh=rbGkDVcvb iV+gJzJYJ9qeYhwYbs=; b=MTuyEUOpaIzrsmBT26mH16JMJE11acdqqCG3NFbUM pxsXssfz3pXPaSwOBG06Df0j7QgDTta9Sy6KLw6eGCtcd61UXz7zeh8Fy9uR4oTe Tevbo/W6DeJOBzs5GJvlsIpCIbh4a48no26SQXJwXZQuGtr8rLGk6sPjgT45MmtG ow= Received: (qmail 52390 invoked by alias); 15 Sep 2015 09:16:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 52298 invoked by uid 89); 15 Sep 2015 09:16:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 15 Sep 2015 09:16:12 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-24-B62gHG_oQLSrIRK6IqyNZQ-17; Tue, 15 Sep 2015 10:14:59 +0100 Received: from arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 15 Sep 2015 10:14:54 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com Subject: [PATCH][AArch64 array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P Date: Tue, 15 Sep 2015 10:14:43 +0100 Message-Id: <1442308483-21714-9-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> References: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> X-MC-Unique: B62gHG_oQLSrIRK6IqyNZQ-17 X-IsSubscribed: yes This adds an AARCH64_VALID_SIMD_DREG_MODE exactly paralleling the existing ...QREG... macro. The new test now compiles (at -O3) to: test_1: add v1.2s, v1.2s, v5.2s add v2.2s, v2.2s, v6.2s add v3.2s, v3.2s, v7.2s add v0.2s, v0.2s, v4.2s ret Whereas prior to this patch we got: test_1: add v0.2s, v0.2s, v4.2s sub sp, sp, #160 add v1.2s, v1.2s, v5.2s add v2.2s, v2.2s, v6.2s add v3.2s, v3.2s, v7.2s str d0, [sp, 96] str d1, [sp, 104] str d2, [sp, 112] str d3, [sp, 120] ldp x2, x3, [sp, 96] stp x2, x3, [sp, 128] ldp x0, x1, [sp, 112] stp x0, x1, [sp, 144] ldr d1, [sp, 136] ldr d0, [sp, 128] ldr d2, [sp, 144] ldr d3, [sp, 152] add sp, sp, 160 ret I've tried to look for (the absence of) this extra code in a number of ways, all 3 scan...not's were previously failing (i.e. regex's were matching) but now pass. bootstrapped and check-gcc on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New. (AARCH64_VALID_SIMD_QREG_MODE): Correct mode->MODE. * config/aarch64/aarch64.c (aarch64_array_mode_supported_p): Add AARCH64_VALID_SIMD_DREG_MODE. gcc/testsuite/ChangeLog: * gcc.target/aarch64/vect-int32x2x4_1.c: New. --- gcc/config/aarch64/aarch64.c | 3 ++- gcc/config/aarch64/aarch64.h | 6 ++++++ .../gcc.target/aarch64/vect-int32x2x4_1.c | 22 ++++++++++++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-int32x2x4_1.c diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 0d36ee5..5f5d14c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -677,7 +677,8 @@ aarch64_array_mode_supported_p (machine_mode mode, unsigned HOST_WIDE_INT nelems) { if (TARGET_SIMD - && AARCH64_VALID_SIMD_QREG_MODE (mode) + && (AARCH64_VALID_SIMD_QREG_MODE (mode) + || AARCH64_VALID_SIMD_DREG_MODE (mode)) && (nelems >= 2 && nelems <= 4)) return true; diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 9669e01..5a8db76 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -872,6 +872,12 @@ extern enum aarch64_code_model aarch64_cmodel; (aarch64_cmodel == AARCH64_CMODEL_TINY \ || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) +/* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ +#define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ + ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ + || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ + || (MODE) == DFmode) + /* Modes valid for AdvSIMD Q registers. */ #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-int32x2x4_1.c b/gcc/testsuite/gcc.target/aarch64/vect-int32x2x4_1.c new file mode 100644 index 0000000..734cfd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-int32x2x4_1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fdump-rtl-expand" } */ + +#include + +uint32x2x4_t +test_1 (uint32x2x4_t a, uint32x2x4_t b) +{ + uint32x2x4_t result; + + for (unsigned index = 0; index < 4; ++index) + result.val[index] = a.val[index] + b.val[index]; + + return result; +} + +/* Should not use the stack in expand. */ +/* { dg-final { scan-rtl-dump-not "virtual-stack-vars" "expand" } } */ +/* Should not have to modify the stack pointer. */ +/* { dg-final { scan-assembler-not "\t(add|sub).*sp" } } */ +/* Should not have to store or load anything. */ +/* { dg-final { scan-assembler-not "\t(ld|st)\[rp\]" } } */