From patchwork Tue Sep 15 09:14:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 517750 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6195F1401CD for ; Tue, 15 Sep 2015 19:15:48 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=VsIM3kc3; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; q=dns; s=default; b=TEa 8FmH9E1k9twkoVFcVNrTjnnL2n9byOH9lCE6WielCZO3NwDbbWtYISEKqhDllaaZ RNgdeBaD7J8JpYiZj06Lf3xI3mjGmZLE4vC4WiVvPgVhlXtSxLjOEAZSqNxhlSlU m4P+moYE8htBkRDBJggUQpKlreglpoGCdmLm30ZU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; s=default; bh=zSgwrTkyb P4x7RwfrF1Fzv6z3IE=; b=VsIM3kc3H/nt93qccu04JPWESMUxukBWOWxKCvB13 Q8Hl5M35xdRBb/ozngl2vvoIP6PGEJywKsegMCdKa6TXLDnn2wTXEji5VOYeALCK a9ruvb9wKOZy16Xm5FOhalwITWxrH+b7GalUmBWR84phKBWIz2mG6cA9PNaQVvgC Oo= Received: (qmail 45344 invoked by alias); 15 Sep 2015 09:15:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 45159 invoked by uid 89); 15 Sep 2015 09:15:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.9 required=5.0 tests=AWL, BAYES_00, MEDICAL_SUBJECT, SPF_PASS autolearn=no version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 15 Sep 2015 09:15:01 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-24-SHfV9ixWTbOwZllfjkCB-Q-7; Tue, 15 Sep 2015 10:14:56 +0100 Received: from arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 15 Sep 2015 10:14:54 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com Subject: [PATCH][AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md Date: Tue, 15 Sep 2015 10:14:38 +0100 Message-Id: <1442308483-21714-4-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> References: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> X-MC-Unique: SHfV9ixWTbOwZllfjkCB-Q-7 X-IsSubscribed: yes The V_THREE_ELEM attribute used BLKmode for most sizes, but occasionally EImode. This patch changes to BLKmode in all cases, explicitly setting memory size (thus, preserving size for the cases that were EImode, and setting size for the first time for cases that were already BLKmode). The patterns affected are only for intrinsics: the aarch64_ld3r expanders and aarch64_simd_ld3r insns, and the aarch64_vec_{load,store}_lanesci_lane insns used by the aarch64_{ld,st}3_lane expanders. bootstrapped and check-gcc on aarch64-none-linux-gnu gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_simd_ld3r, aarch64_vec_load_lanesci_lane, aarch64_vec_store_lanesci_lane): Change operand mode from to BLK. (aarch64_ld3r, aarch64_ld3_lane, aarch64_st3_lane): Generate MEM rtx with BLKmode, call set_mem_size. * config/aarch64/iterators.md (V_THREE_ELEM): Remove. --- gcc/config/aarch64/aarch64-simd.md | 26 +++++++++++++------------- gcc/config/aarch64/iterators.md | 9 --------- 2 files changed, 13 insertions(+), 22 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 20b9be9..c1048d3 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4026,7 +4026,7 @@ (define_insn "aarch64_simd_ld3r" [(set (match_operand:CI 0 "register_operand" "=w") - (unspec:CI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD3_DUP))] "TARGET_SIMD" @@ -4036,7 +4036,7 @@ (define_insn "aarch64_vec_load_lanesci_lane" [(set (match_operand:CI 0 "register_operand" "=w") - (unspec:CI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (match_operand:CI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4080,11 +4080,11 @@ ;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "aarch64_vec_store_lanesci_lane" - [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") - (unspec: [(match_operand:CI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) - (match_operand:SI 2 "immediate_operand" "i")] - UNSPEC_ST3_LANE))] + [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:BLK [(match_operand:CI 1 "register_operand" "w") + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_ST3_LANE))] "TARGET_SIMD" { operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); @@ -4400,8 +4400,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); emit_insn (gen_aarch64_simd_ld3r (operands[0], mem)); DONE; @@ -4625,8 +4625,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); emit_insn (gen_aarch64_vec_load_lanesci_lane (operands[0], mem, @@ -4905,8 +4905,8 @@ (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[0]); + rtx mem = gen_rtx_MEM (BLKmode, operands[0]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); emit_insn (gen_aarch64_vec_store_lanesci_lane (mem, operands[1], diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 298bee6..65ca0fd 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -601,15 +601,6 @@ (V4HF "SF") (V8HF "SF") (DF "V2DI") (V2DF "V2DI")]) -;; Similar, for three elements. -(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK") - (V4HI "BLK") (V8HI "BLK") - (V2SI "BLK") (V4SI "BLK") - (DI "EI") (V2DI "EI") - (V2SF "BLK") (V4SF "BLK") - (V4HF "BLK") (V8HF "BLK") - (DF "EI") (V2DF "EI")]) - ;; Similar, for four elements. (define_mode_attr V_FOUR_ELEM [(V8QI "SI") (V16QI "SI") (V4HI "V4HI") (V8HI "V4HI")