From patchwork Tue Sep 15 09:14:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 517757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C4D361402BC for ; Tue, 15 Sep 2015 19:17:32 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=xdMWcL23; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; q=dns; s=default; b=gvY caAeAuK223Pl0BnbDVUlh38oeaZcSzbpRxu884qdV1OILv3max1LzsQMIiPdS2on VNhcayGyPk510+rSM6V0lAUs/18XGi3wGmvK26ke221Iazyez7CuS4+yBRep5nnc Ym3zOR7eVtqqDUJTlPyRSKaCqzvWNY4qvZf2e7f8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; s=default; bh=NLwa7kqbL fkYsgclpdUNU0A+g9M=; b=xdMWcL23Ss/sqv+jXZ4EONvvkMlDomvSlgrQc5azP EoCFsPXzmv9Tx6H1boUtfaSW9AGGPeTCv/NthqN/1F2RTZXC5emztkwH5slvwAjw +Y4cnljsE/WUChGYtkewK7cBvcx3zCGMO5UVa+xPyEzD8vuqrJ23HtzT8kSpmtvG Gc= Received: (qmail 52424 invoked by alias); 15 Sep 2015 09:16:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 52326 invoked by uid 89); 15 Sep 2015 09:16:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=AWL, BAYES_00, SPF_SOFTFAIL autolearn=no version=3.3.2 X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 15 Sep 2015 09:16:12 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZbmLQ-0002oc-DC for gcc-patches@gcc.gnu.org; Tue, 15 Sep 2015 05:16:10 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([146.101.78.143]:43817) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbmLQ-0002oP-5R for gcc-patches@gcc.gnu.org; Tue, 15 Sep 2015 05:16:08 -0400 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-24-DyPdjYhmTcKEnxg7vb7Qlg-3; Tue, 15 Sep 2015 10:14:54 +0100 Received: from arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 15 Sep 2015 10:14:54 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com Subject: [PATCH][AArch64 array_mode 1/8] Rename vec_store_lanes_lane to aarch64_vec_store_lanes_lane Date: Tue, 15 Sep 2015 10:14:36 +0100 Message-Id: <1442308483-21714-2-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> References: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> X-MC-Unique: DyPdjYhmTcKEnxg7vb7Qlg-3 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 146.101.78.143 X-IsSubscribed: yes vec_store_lanes{oi,ci,xi}_lane are not standard pattern names, so using them in aarch64-simd.md is misleading. This adds an aarch64_ prefix to those pattern names, paralleling aarch64_vec_load_lanes_lane. bootstrapped and check-gcc on aarch64-none-linux-gnu gcc/ChangeLog: * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane): Rename to... (aarch64_vec_store_lanesoi_lane): ...this. (vec_store_lanesci_lane): Rename to... (aarch64_vec_store_lanesci_lane): ...this. (vec_store_lanesxi_lane): Rename to... (aarch64_vec_store_lanesxi_lane): ...this. (aarch64_st2_lane, aarch64_st3_lane, aarch64_st4_lane): Follow renaming. --- gcc/config/aarch64/aarch64-simd.md | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index a4eaeca..67cb4c9b 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3981,7 +3981,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesoi_lane" +(define_insn "aarch64_vec_store_lanesoi_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:OI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4079,7 +4079,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesci_lane" +(define_insn "aarch64_vec_store_lanesci_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:CI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4177,7 +4177,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesxi_lane" +(define_insn "aarch64_vec_store_lanesxi_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:XI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4886,7 +4886,9 @@ machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - emit_insn (gen_vec_store_lanesoi_lane (mem, operands[1], operands[2])); + emit_insn (gen_aarch64_vec_store_lanesoi_lane (mem, + operands[1], + operands[2])); DONE; }) @@ -4900,7 +4902,9 @@ machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - emit_insn (gen_vec_store_lanesci_lane (mem, operands[1], operands[2])); + emit_insn (gen_aarch64_vec_store_lanesci_lane (mem, + operands[1], + operands[2])); DONE; }) @@ -4914,7 +4918,9 @@ machine_mode mode = mode; rtx mem = gen_rtx_MEM (mode, operands[0]); - emit_insn (gen_vec_store_lanesxi_lane (mem, operands[1], operands[2])); + emit_insn (gen_aarch64_vec_store_lanesxi_lane (mem, + operands[1], + operands[2])); DONE; })