diff mbox

[AArch64,array_mode,7/8] Combine the expanders using VSTRUCT:nregs

Message ID 1440596819-18018-8-git-send-email-alan.lawrence@arm.com
State New
Headers show

Commit Message

Alan Lawrence Aug. 26, 2015, 1:46 p.m. UTC 
The previous patches leave ld[234]_lane, st[234]_lane, and ld[234]r expanders all nearly identical, so we can easily parameterize across the number of lanes and combine them.

For the ld<VSTRUCT:nregs>_lane pattern, I switched from the VCONQ attribute to just using the MODE attribute, this is identical for all the Q-register modes over which we iterate.

bootstrapped and check-gcc on aarch64-none-linux-gnu

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_ld2r<mode>,
	aarch64_ld3r<mode>, aarch64_ld4r<mode>): Combine together, making...
	(aarch64_simd_ld<VSTRUCT:nregs>r<VALLDIF:mode>): ...this.

	(aarch64_ld2_lane<mode>, aarch64_ld3_lane<mode>,
	aarch64_ld4_lane<mode>): Combine together, making...
	(aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>): ...this.

	(aarch64_st2_lane<VQ:mode>, aarch64_st3_lane<VQ:mode>,
	aarch64_st4_lane<VQ:mode>): Combine together, making...
	(aarch64_st<VSTRUCT:nregs>_lane<VQ:mode>): ...this.
---
 gcc/config/aarch64/aarch64-simd.md | 144 ++++++-------------------------------
 1 file changed, 21 insertions(+), 123 deletions(-)
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index f938754..38c4210 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4349,42 +4349,18 @@ 
     FAIL;
 })
 
-(define_expand "aarch64_ld2r<mode>"
-  [(match_operand:OI 0 "register_operand" "=w")
+(define_expand "aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>"
+  [(match_operand:VSTRUCT 0 "register_operand" "=w")
    (match_operand:DI 1 "register_operand" "w")
    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
   rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<VALLDIF:MODE>mode))
+		     * <VSTRUCT:nregs>);
 
-  emit_insn (gen_aarch64_simd_ld2r<mode> (operands[0], mem));
-  DONE;
-})
-
-(define_expand "aarch64_ld3r<mode>"
-  [(match_operand:CI 0 "register_operand" "=w")
-   (match_operand:DI 1 "register_operand" "w")
-   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
-  "TARGET_SIMD"
-{
-  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
-
-  emit_insn (gen_aarch64_simd_ld3r<mode> (operands[0], mem));
-  DONE;
-})
-
-(define_expand "aarch64_ld4r<mode>"
-  [(match_operand:XI 0 "register_operand" "=w")
-   (match_operand:DI 1 "register_operand" "w")
-   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
-  "TARGET_SIMD"
-{
-  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
-
-  emit_insn (gen_aarch64_simd_ld4r<mode> (operands[0],mem));
+  emit_insn (gen_aarch64_simd_ld<VSTRUCT:nregs>r<VALLDIF:mode> (operands[0],
+								mem));
   DONE;
 })
 
@@ -4561,67 +4537,25 @@ 
   DONE;
 })
 
-(define_expand "aarch64_ld2_lane<mode>"
-  [(match_operand:OI 0 "register_operand" "=w")
+(define_expand "aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>"
+  [(match_operand:VSTRUCT 0 "register_operand" "=w")
 	(match_operand:DI 1 "register_operand" "w")
-	(match_operand:OI 2 "register_operand" "0")
+	(match_operand:VSTRUCT 2 "register_operand" "0")
 	(match_operand:SI 3 "immediate_operand" "i")
 	(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
   rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<VQ:MODE>mode))
+		     * <VSTRUCT:nregs>);
 
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
+  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VQ:MODE>mode),
 			    NULL);
-  emit_insn (gen_aarch64_vec_load_lanesoi_lane<mode> (operands[0],
-						      mem,
-						      operands[2],
-						      operands[3]));
+  emit_insn (gen_aarch64_vec_load_lanes<VSTRUCT:mode>_lane<VQ:mode> (
+	operands[0], mem, operands[2], operands[3]));
   DONE;
 })
 
-(define_expand "aarch64_ld3_lane<mode>"
-  [(match_operand:CI 0 "register_operand" "=w")
-	(match_operand:DI 1 "register_operand" "w")
-	(match_operand:CI 2 "register_operand" "0")
-	(match_operand:SI 3 "immediate_operand" "i")
-	(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
-  "TARGET_SIMD"
-{
-  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
-
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
-			    NULL);
-  emit_insn (gen_aarch64_vec_load_lanesci_lane<mode> (operands[0],
-						      mem,
-						      operands[2],
-						      operands[3]));
-  DONE;
-})
-
-(define_expand "aarch64_ld4_lane<mode>"
-  [(match_operand:XI 0 "register_operand" "=w")
-	(match_operand:DI 1 "register_operand" "w")
-	(match_operand:XI 2 "register_operand" "0")
-	(match_operand:SI 3 "immediate_operand" "i")
-	(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
-  "TARGET_SIMD"
-{
-  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
-
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
-			    NULL);
-  emit_insn (gen_aarch64_vec_load_lanesxi_lane<mode> (operands[0],
-						      mem,
-						      operands[2],
-						      operands[3]));
-  DONE;
-})
-
-
 
 ;; Expanders for builtins to extract vector registers from large
 ;; opaque integer modes.
@@ -4850,57 +4784,21 @@ 
   DONE;
 })
 
-(define_expand "aarch64_st2_lane<VQ:mode>"
+(define_expand "aarch64_st<VSTRUCT:nregs>_lane<VQ:mode>"
  [(match_operand:DI 0 "register_operand" "r")
-  (match_operand:OI 1 "register_operand" "w")
-  (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-  (match_operand:SI 2 "immediate_operand")]
-  "TARGET_SIMD"
-{
-  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
-
-  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
-
-  emit_insn (gen_aarch64_vec_store_lanesoi_lane<VQ:mode> (mem,
-							  operands[1],
-							  operands[2]));
-  DONE;
-})
-
-(define_expand "aarch64_st3_lane<VQ:mode>"
- [(match_operand:DI 0 "register_operand" "r")
-  (match_operand:CI 1 "register_operand" "w")
-  (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-  (match_operand:SI 2 "immediate_operand")]
-  "TARGET_SIMD"
-{
-  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3);
-
-  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
-
-  emit_insn (gen_aarch64_vec_store_lanesci_lane<VQ:mode> (mem,
-							  operands[1],
-							  operands[2]));
-  DONE;
-})
-
-(define_expand "aarch64_st4_lane<VQ:mode>"
- [(match_operand:DI 0 "register_operand" "r")
-  (match_operand:XI 1 "register_operand" "w")
+  (match_operand:VSTRUCT 1 "register_operand" "w")
   (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
   (match_operand:SI 2 "immediate_operand")]
   "TARGET_SIMD"
 {
   rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
-  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<VQ:MODE>mode))
+		     * <VSTRUCT:nregs>);
 
-  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+  operands[2] = GEN_INT (ENDIAN_LANE_N (<VQ:MODE>mode, INTVAL (operands[2])));
 
-  emit_insn (gen_aarch64_vec_store_lanesxi_lane<VQ:mode> (mem,
-							  operands[1],
-							  operands[2]));
+  emit_insn (gen_aarch64_vec_store_lanes<VSTRUCT:mode>_lane<VQ:mode> (
+		mem, operands[1], operands[2]));
   DONE;
 })