From patchwork Wed Aug 26 13:46:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 510879 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D10CA140332 for ; Wed, 26 Aug 2015 23:48:49 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=o2mwculd; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=CHvIjhJTwKdqQNXSljz8qkfWnlSZWRjRa20ihShKXp+wAZU8/3mVg 4065v1BPp3umb9zwPRvRPBzOf8Rd2zTaQRb5tCrIE0zYzd3Oohb5GZQfkvL8eCxU 2RGfgntKhuiqDE+IMaQ2ITlbFSiTVgIb5ivYkXbIV2OKpBwjKPGtmU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=mXIdQ9veR/qVFRKs8qVvXm/YCQ0=; b=o2mwculdTYWhqNqhcpRk WcEhjqeoGMetFidqKnLcxWmEzVnLe+Fod6kKFuZaRl7X1JjQ7iTz/DoPKZdpg7Qs ewtQKpDiHsMDH7CJWAU6ZXdk/ivYFtgPTDYBW2KL+W6V61w25D5p6kfQVq03MJdM r0F3PO4tO40x8BNcEbrF9bs= Received: (qmail 40587 invoked by alias); 26 Aug 2015 13:47:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 40537 invoked by uid 89); 26 Aug 2015 13:47:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM autolearn=no version=3.3.2 X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 26 Aug 2015 13:47:17 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZUb2k-0006DQ-KJ for gcc-patches@gcc.gnu.org; Wed, 26 Aug 2015 09:47:15 -0400 Received: from fw-tnat.cambridge.arm.com ([217.140.96.140]:27481 helo=cam-smtp0.cambridge.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUb2k-0006DB-Ax for gcc-patches@gcc.gnu.org; Wed, 26 Aug 2015 09:47:10 -0400 Received: from e104536-lin.cambridge.arm.com (e104536-lin.cambridge.arm.com [10.2.207.65]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id t7QDl7fS025849; Wed, 26 Aug 2015 14:47:07 +0100 Received: from e104536-lin.cambridge.arm.com (localhost [127.0.0.1]) by e104536-lin.cambridge.arm.com (8.13.8/8.11.6) with ESMTP id t7QDl7cF018104; Wed, 26 Aug 2015 14:47:07 +0100 Received: (from alalaw01@localhost) by e104536-lin.cambridge.arm.com (8.13.8/8.13.8/Submit) id t7QDl78D018103; Wed, 26 Aug 2015 14:47:07 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [PATCH][AArch64 array_mode 5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size. Date: Wed, 26 Aug 2015 14:46:56 +0100 Message-Id: <1440596819-18018-6-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> References: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 217.140.96.140 X-IsSubscribed: yes This removes V_FOUR_ELEM in the same way that patch 3 removed V_THREE_ELEM, again using BLKmode + set_mem_size. (This makes the four-lane expanders very similar to the three-lane expanders, and they will be combined in patch 7.) bootstrapped and check-gcc on aarch64-none-linux-gnu gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_simd_ld4r, aarch64_vec_load_lanesxi_lane, aarch64_vec_store_lanesxi_lane to BLK. (aarch64_ld4r, aarch64_ld4_lane, aarch64_st4_lane): Generate MEM rtx with BLKmode, call set_mem_size. * config/aarch64/iterators.md (V_FOUR_ELEM): Remove. --- gcc/config/aarch64/aarch64-simd.md | 25 +++++++++++++------------ gcc/config/aarch64/iterators.md | 9 --------- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 156fc4f..68182d6 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4096,7 +4096,7 @@ (define_insn "aarch64_simd_ld4r" [(set (match_operand:XI 0 "register_operand" "=w") - (unspec:XI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:XI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD4_DUP))] "TARGET_SIMD" @@ -4106,7 +4106,7 @@ (define_insn "aarch64_vec_load_lanesxi_lane" [(set (match_operand:XI 0 "register_operand" "=w") - (unspec:XI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:XI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (match_operand:XI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4147,10 +4147,10 @@ ;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "aarch64_vec_store_lanesxi_lane" - [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") - (unspec: [(match_operand:XI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) - (match_operand:SI 2 "immediate_operand" "i")] + [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:BLK [(match_operand:XI 1 "register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST4_LANE))] "TARGET_SIMD" { @@ -4381,8 +4381,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); emit_insn (gen_aarch64_simd_ld4r (operands[0],mem)); DONE; @@ -4609,8 +4609,8 @@ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode), NULL); @@ -4892,8 +4892,9 @@ (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[0]); + rtx mem = gen_rtx_MEM (BLKmode, operands[0]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); emit_insn (gen_aarch64_vec_store_lanesxi_lane (mem, diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index ae0be0b..9535b7f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -568,15 +568,6 @@ (V2SF "V2SF") (V4SF "V2SF") (DF "V2DI") (V2DF "V2DI")]) -;; Similar, for four elements. -(define_mode_attr V_FOUR_ELEM [(V8QI "SI") (V16QI "SI") - (V4HI "V4HI") (V8HI "V4HI") - (V2SI "V4SI") (V4SI "V4SI") - (DI "OI") (V2DI "OI") - (V2SF "V4SF") (V4SF "V4SF") - (DF "OI") (V2DF "OI")]) - - ;; Mode for atomic operation suffixes (define_mode_attr atomic_sfx [(QI "b") (HI "h") (SI "") (DI "")])