From patchwork Wed Aug 26 13:46:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 510878 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7469E1401F0 for ; Wed, 26 Aug 2015 23:48:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=R4CLTTrA; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=hXay1sAcAXAyy+5c+2vrGmBYmmavnCJIKuRhtqo9Z+pIfm6ES7Vc3 iBHUiFYlUy6D0rmL9dsv+Q1anPKWNtVMozQh1gkTxQN9pTdB2Y+D95CdWwPFBTiH KSYqjmaIMd9Wo5xczInxTR+U5yuT3zmcZBvqFgGEUy8ngTW/DUEXQ8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=KiK0MleyzfRS/cp08EGF63nC/6I=; b=R4CLTTrA3WGutF2bozfA Qs4yqT+38u5lArerHphq3+cSpwGA5JHHsWF3Mf7LEpDJ66nhDeZkTeMI29yiVDGw 6cgt94xPaVA96H9rei3gd7dS1EIsPHhGfvsBJ0fvm/KEEKgiNiBovJJTgzNdze7p 2FI0yoJaMk6VSyGxJMlzM+Y= Received: (qmail 39630 invoked by alias); 26 Aug 2015 13:47:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 39430 invoked by uid 89); 26 Aug 2015 13:47:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.4 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, MEDICAL_SUBJECT, NO_DNS_FOR_FROM autolearn=no version=3.3.2 X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 26 Aug 2015 13:47:17 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZUb2k-0006DV-Kj for gcc-patches@gcc.gnu.org; Wed, 26 Aug 2015 09:47:15 -0400 Received: from fw-tnat.cambridge.arm.com ([217.140.96.140]:36152 helo=cam-smtp0.cambridge.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUb2k-0006DA-B3 for gcc-patches@gcc.gnu.org; Wed, 26 Aug 2015 09:47:10 -0400 Received: from e104536-lin.cambridge.arm.com (e104536-lin.cambridge.arm.com [10.2.207.65]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id t7QDl7fH025843; Wed, 26 Aug 2015 14:47:07 +0100 Received: from e104536-lin.cambridge.arm.com (localhost [127.0.0.1]) by e104536-lin.cambridge.arm.com (8.13.8/8.11.6) with ESMTP id t7QDl7Kk018096; Wed, 26 Aug 2015 14:47:07 +0100 Received: (from alalaw01@localhost) by e104536-lin.cambridge.arm.com (8.13.8/8.13.8/Submit) id t7QDl7iY018095; Wed, 26 Aug 2015 14:47:07 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [PATCH][AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md Date: Wed, 26 Aug 2015 14:46:54 +0100 Message-Id: <1440596819-18018-4-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> References: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 217.140.96.140 X-IsSubscribed: yes The V_THREE_ELEM attribute used BLKmode for most sizes, but occasionally EImode. This patch changes to BLKmode in all cases, explicitly setting memory size (thus, preserving size for the cases that were EImode, and setting size for the first time for cases that were already BLKmode). The patterns affected are only for intrinsics: the aarch64_ld3r expanders and aarch64_simd_ld3r insns, and the aarch64_vec_{load,store}_lanesci_lane insns used by the aarch64_{ld,st}3_lane expanders. bootstrapped and check-gcc on aarch64-none-linux-gnu gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_simd_ld3r, aarch64_vec_load_lanesci_lane, aarch64_vec_store_lanesci_lane): Change operand mode from to BLK. (aarch64_ld3r, aarch64_ld3_lane, aarch64_st3_lane): Generate MEM rtx with BLKmode, call set_mem_size. * config/aarch64/iterators.md (V_THREE_ELEM): Remove. --- gcc/config/aarch64/aarch64-simd.md | 27 ++++++++++++++------------- gcc/config/aarch64/iterators.md | 8 -------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7b7a1b8..156fc4f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4001,7 +4001,7 @@ (define_insn "aarch64_simd_ld3r" [(set (match_operand:CI 0 "register_operand" "=w") - (unspec:CI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD3_DUP))] "TARGET_SIMD" @@ -4011,7 +4011,7 @@ (define_insn "aarch64_vec_load_lanesci_lane" [(set (match_operand:CI 0 "register_operand" "=w") - (unspec:CI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (match_operand:CI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4052,11 +4052,11 @@ ;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "aarch64_vec_store_lanesci_lane" - [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") - (unspec: [(match_operand:CI 1 "register_operand" "w") - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) - (match_operand:SI 2 "immediate_operand" "i")] - UNSPEC_ST3_LANE))] + [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:BLK [(match_operand:CI 1 "register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_ST3_LANE))] "TARGET_SIMD" { operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); @@ -4368,8 +4368,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); emit_insn (gen_aarch64_simd_ld3r (operands[0], mem)); DONE; @@ -4589,8 +4589,8 @@ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode), NULL); @@ -4874,8 +4874,9 @@ (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[0]); + rtx mem = gen_rtx_MEM (BLKmode, operands[0]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); emit_insn (gen_aarch64_vec_store_lanesci_lane (mem, diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 98b6714..ae0be0b 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -568,14 +568,6 @@ (V2SF "V2SF") (V4SF "V2SF") (DF "V2DI") (V2DF "V2DI")]) -;; Similar, for three elements. -(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK") - (V4HI "BLK") (V8HI "BLK") - (V2SI "BLK") (V4SI "BLK") - (DI "EI") (V2DI "EI") - (V2SF "BLK") (V4SF "BLK") - (DF "EI") (V2DF "EI")]) - ;; Similar, for four elements. (define_mode_attr V_FOUR_ELEM [(V8QI "SI") (V16QI "SI") (V4HI "V4HI") (V8HI "V4HI")