| Message ID | 1440596819-18018-2-git-send-email-alan.lawrence@arm.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Aug 26, 2015 at 02:46:52PM +0100, Alan Lawrence wrote: > vec_store_lanes{oi,ci,xi}_lane are not standard pattern names, so using them > in aarch64-simd.md is misleading. This adds an aarch64_ prefix to those > pattern names, paralleling aarch64_vec_load_lanes<mode>_lane. > > bootstrapped and check-gcc on aarch64-none-linux-gnu OK. (The patch doesn't apply to trunk as is, but the rebase is easy enough and also OK). Thanks, James > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Rename > to... > (aarch64_vec_store_lanesoi_lane<mode>): ...this. > > (vec_store_lanesci_lane<mode>): Rename to... > (aarch64_vec_store_lanesci_lane<mode>): ...this. > > (vec_store_lanesxi_lane<mode>): Rename to... > (aarch64_vec_store_lanesxi_lane<mode>): ...this. > > (aarch64_st2_lane<VQ:mode>, aarch64_st3_lane<VQ:mode>, > aarch64_st4_lane<VQ:mode>): Follow renaming. > --- > gcc/config/aarch64/aarch64-simd.md | 24 ++++++++++++------------ > 1 file changed, 12 insertions(+), 12 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index b90f938..3796386 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -3956,7 +3956,7 @@ > ) > > ;; RTL uses GCC vector extension indices, so flip only for assembly. > -(define_insn "vec_store_lanesoi_lane<mode>" > +(define_insn "aarch64_vec_store_lanesoi_lane<mode>" > [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") > (unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w") > (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) > @@ -4051,7 +4051,7 @@ > ) > > ;; RTL uses GCC vector extension indices, so flip only for assembly. > -(define_insn "vec_store_lanesci_lane<mode>" > +(define_insn "aarch64_vec_store_lanesci_lane<mode>" > [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") > (unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w") > (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) > @@ -4146,7 +4146,7 @@ > ) > > ;; RTL uses GCC vector extension indices, so flip only for assembly. > -(define_insn "vec_store_lanesxi_lane<mode>" > +(define_insn "aarch64_vec_store_lanesxi_lane<mode>" > [(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") > (unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w") > (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) > @@ -4861,9 +4861,9 @@ > rtx mem = gen_rtx_MEM (mode, operands[0]); > operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); > > - emit_insn (gen_vec_store_lanesoi_lane<VQ:mode> (mem, > - operands[1], > - operands[2])); > + emit_insn (gen_aarch64_vec_store_lanesoi_lane<VQ:mode> (mem, > + operands[1], > + operands[2])); > DONE; > }) > > @@ -4878,9 +4878,9 @@ > rtx mem = gen_rtx_MEM (mode, operands[0]); > operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); > > - emit_insn (gen_vec_store_lanesci_lane<VQ:mode> (mem, > - operands[1], > - operands[2])); > + emit_insn (gen_aarch64_vec_store_lanesci_lane<VQ:mode> (mem, > + operands[1], > + operands[2])); > DONE; > }) > > @@ -4895,9 +4895,9 @@ > rtx mem = gen_rtx_MEM (mode, operands[0]); > operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); > > - emit_insn (gen_vec_store_lanesxi_lane<VQ:mode> (mem, > - operands[1], > - operands[2])); > + emit_insn (gen_aarch64_vec_store_lanesxi_lane<VQ:mode> (mem, > + operands[1], > + operands[2])); > DONE; > }) > > -- > 1.8.3 >
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b90f938..3796386 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3956,7 +3956,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesoi_lane<mode>" +(define_insn "aarch64_vec_store_lanesoi_lane<mode>" [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4051,7 +4051,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesci_lane<mode>" +(define_insn "aarch64_vec_store_lanesci_lane<mode>" [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4146,7 +4146,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesxi_lane<mode>" +(define_insn "aarch64_vec_store_lanesxi_lane<mode>" [(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4861,9 +4861,9 @@ rtx mem = gen_rtx_MEM (mode, operands[0]); operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesoi_lane<VQ:mode> (mem, - operands[1], - operands[2])); + emit_insn (gen_aarch64_vec_store_lanesoi_lane<VQ:mode> (mem, + operands[1], + operands[2])); DONE; }) @@ -4878,9 +4878,9 @@ rtx mem = gen_rtx_MEM (mode, operands[0]); operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesci_lane<VQ:mode> (mem, - operands[1], - operands[2])); + emit_insn (gen_aarch64_vec_store_lanesci_lane<VQ:mode> (mem, + operands[1], + operands[2])); DONE; }) @@ -4895,9 +4895,9 @@ rtx mem = gen_rtx_MEM (mode, operands[0]); operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesxi_lane<VQ:mode> (mem, - operands[1], - operands[2])); + emit_insn (gen_aarch64_vec_store_lanesxi_lane<VQ:mode> (mem, + operands[1], + operands[2])); DONE; })
vec_store_lanes{oi,ci,xi}_lane are not standard pattern names, so using them in aarch64-simd.md is misleading. This adds an aarch64_ prefix to those pattern names, paralleling aarch64_vec_load_lanes<mode>_lane. bootstrapped and check-gcc on aarch64-none-linux-gnu gcc/ChangeLog: * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Rename to... (aarch64_vec_store_lanesoi_lane<mode>): ...this. (vec_store_lanesci_lane<mode>): Rename to... (aarch64_vec_store_lanesci_lane<mode>): ...this. (vec_store_lanesxi_lane<mode>): Rename to... (aarch64_vec_store_lanesxi_lane<mode>): ...this. (aarch64_st2_lane<VQ:mode>, aarch64_st3_lane<VQ:mode>, aarch64_st4_lane<VQ:mode>): Follow renaming. --- gcc/config/aarch64/aarch64-simd.md | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-)