From patchwork Tue Jul 28 16:38:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Ellcey X-Patchwork-Id: 501303 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 336BD140AF3 for ; Wed, 29 Jul 2015 02:39:01 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=coKwKOef; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:reply-to:to:cc:date:content-type :mime-version; q=dns; s=default; b=qJeAiSGh9XlIz+T+tCNfpX5rnfFMw uMg7IUzWNUmte2nkxH9XtXnE6+ZcbojpQ2qICi90P+TQjaIX2sYql7OYV8jkai75 RtEMT6DCt6tT0QNKNmOKZ8XVDiyyJnHDOd5vH9v73NPk6S0XjOm3nhoEjvI0feQs VRLJqjAaT0fL04= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:reply-to:to:cc:date:content-type :mime-version; s=default; bh=n/JZ/PWvos31X0bP0qbDoDO8Qx8=; b=coK wKOef7wCccNzCF70QEwvtWCx9R4TlZtn1E+hxtSgdBb0KuE+cbl5DWEqhmWKcoci SrU5Ob9urAwYl+PocYkRcbZPGL9Q+zieDpkKbUJz+1XMmM0z6dMdOFDziuXCSLLE z2OPOuLoaXwifM1Zqi7tx3WghVAfnwVh4QnQB42A= Received: (qmail 44042 invoked by alias); 28 Jul 2015 16:38:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 44027 invoked by uid 89); 28 Jul 2015 16:38:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=AWL, BAYES_50, KAM_STOCKGEN, RCVD_IN_DNSWL_LOW, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 28 Jul 2015 16:38:49 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id E6BAEF4E9AE13; Tue, 28 Jul 2015 17:38:42 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 28 Jul 2015 17:38:45 +0100 Received: from BAMAIL02.ba.imgtec.org (10.20.40.28) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Tue, 28 Jul 2015 17:38:45 +0100 Received: from [10.20.3.58] (10.20.3.58) by bamail02.ba.imgtec.org (10.20.40.28) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 28 Jul 2015 09:38:42 -0700 Message-ID: <1438101523.19674.219.camel@ubuntu-sellcey> Subject: [Patch, MIPS] MIPS specific optimization for o32 ABI From: Steve Ellcey Reply-To: To: GCC Patches CC: clm , Matthew Fortune Date: Tue, 28 Jul 2015 09:38:43 -0700 MIME-Version: 1.0 This patch implements a MIPS o32 ABI specific optimization called frame header optimization. In the o32 ABI, routines allocate 16 bytes on the stack before calling another routine. This space is used by the callee as space to write the register arguments to if their address is taken. The n32 and n64 ABI's use the more common approach of copying register arguments to local variables if their address is needed. This optimization allows the callee to use that 16 bytes for other purposes if it does not need it to write its arguments out to memory and if it only needs 16 bytes of stack space (or less) for saving callee-saved registers. This can allow us to avoid having to allocate extra stack space in a routine and to remove the stack pointer increment/decrement instructions from the prolog and epilogue which results in a small performance improvement. This patch has been in the Mentor GCC toolchain for MIPS for a while and gotten some testing there and I tested it on the top-of-tree GCC sources with no regressions. OK to checkin? Steve Ellcey sellcey@imgtec.com 2015-07-28 Steve Ellcey Zoran Jovanovic Catherine Moore Tom de Vries * config/mips/mips.opt (mframe-header-opt): New option. * config/mips/mips.c (struct mips_frame_info): Add skip_stack_frame_allocation_p field. (struct machine_function): Add callees_use_frame_header_p, uses_frame_header_p, and initial_total_size fields. (mips_frame_header_usage): New hash. (mips_find_if_frame_header_is_used): New Function. (mips_callee_use_frame_header): New Function. (mips_callees_use_frame_header_p): New Function. (mips_cfun_use_frame_header_p): New Function. (mips_get_updated_offset): New Function. (mips_skip_stack_frame_alloc): New Function. (mips_frame_header_update_insn): New Function. (mips_rest_of_frame_header_opt): New function. (mips_compute_frame_info): Add recalculate and frame arguments. (mips_frame_pointer_required): Add new args to mips_compute_frame_info call. (mips_initial_elimination_offset): Ditto. (mips_gp_expand_needed_p): New function factored out of mips_expand_ghost_gp_insns. (mips_expand_ghost_gp_insns): Use mips_gp_expand_needed_p. (mips_reorg): Use mips_rest_of_frame_header_opt. 2015-07-28 Steve Ellcey Tom de Vries * gcc.target/mips/fho-1.c: New test. * gcc.target/mips/fho-2.c: New test. * gcc.target/mips/mips.exp: Add -mframe-header-opt to mips_option_groups. diff --git a/gcc/testsuite/gcc.target/mips/fho-1.c b/gcc/testsuite/gcc.target/mips/fho-1.c new file mode 100644 index 0000000..e373da4 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/fho-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-options "-mabi=32 -mframe-header-opt -fdump-rtl-mach" } */ +/* Testing -mframe-header-opt optimization option. */ + +NOCOMPRESSION int __attribute__((noinline)) +B (int x) +{ + return x + 3; +} + +/* We are sure that B is not using its incoming stack frame so we can skip + its allocation. */ +NOCOMPRESSION int __attribute__((noinline)) +A (int x) +{ + return B (x) + 2; +} + +NOCOMPRESSION int +main (void) +{ + int a; + void *volatile sp1, *volatile sp2; + register void *sp asm ("$sp"); + sp1 = sp; + a = A (5); + sp2 = sp; + return !(a == 10 && sp1 == sp2); +} + +/* { dg-final { scan-rtl-dump "Frame size reduced by frame header optimization" "mach" } } */ + +/* For enabled targets, test that only one stack allocation is present, the one + in main. The one in A should have been removed by -mframe-header-opt. */ +/* { dg-final { scan-assembler-times "addiu\t\\\$sp,\\\$sp,-" 1 } } */ diff --git a/gcc/testsuite/gcc.target/mips/fho-2.c b/gcc/testsuite/gcc.target/mips/fho-2.c new file mode 100644 index 0000000..d3599b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/fho-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mabi=32 -mframe-header-opt" } */ +/* Testing -mframe-header-opt optimization option. */ + +NOCOMPRESSION int __attribute__((noinline)) +B (int x) +{ + return x + 3; +} + +/* We are sure that B is not using its incoming stack frame so we can skip + its allocation. */ +NOCOMPRESSION int __attribute__((noinline)) +A (int x) +{ + return B (x) + 2; +} + +NOCOMPRESSION int +main (void) +{ + int a; + void *volatile sp1, *volatile sp2; + register void *sp asm ("$sp"); + sp1 = sp; + a = A (5); + sp2 = sp; + return !(a == 10 && sp1 == sp2); +} diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index b3617e4..6e6450e 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -237,6 +237,7 @@ set mips_option_groups { fpu "-m(double|single)-float" forbid_cpu "forbid_cpu=.*" fp "-mfp(32|xx|64)" + frame_header_opt "-mframe-header-opt|-mno-frame-header-opt" gp "-mgp(32|64)" long "-mlong(32|64)" micromips "-mmicromips|-mno-micromips"