From patchwork Thu Jul 2 15:39:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Baylis X-Patchwork-Id: 490685 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1A1191402BA for ; Fri, 3 Jul 2015 01:40:20 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=c+1HGpEt; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=FqUeO22atUF7atHzzq6g4pVVmQ5r3kLCLVpCfNogPXCJ/AQ5MJmNB nMsosyB+LpYUYEpDpMPLG/zvhNuCR9X4ZgJ3idCnwk8+wzj0eVvvRJ4hxoj3FmBx YMz1eLa+1m6PFKrBLWhNTgN0vZmxbvKH2FOvm7OgS6EhTTRT/YLZBY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=lTrvFtL5GXsns7ZvYE1wX/5vlJY=; b=c+1HGpEtPDxqUkFkOvQN YyQQoT4snxDLUHZut+CPWdPMmzWscK0Y1lyGy1xQsgmIiFHHyU4c9VFhL1haCBMh SZ4/csZ4vBBbQW8hA1WbAnjVCNAxD0jWIH1/PDcG6VcLQWZdzxOBX80N+vvd3UyS tIYSBiNf17qPP1uC7OsZXtk= Received: (qmail 121253 invoked by alias); 2 Jul 2015 15:40:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 121199 invoked by uid 89); 2 Jul 2015 15:39:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f44.google.com Received: from mail-wg0-f44.google.com (HELO mail-wg0-f44.google.com) (74.125.82.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 02 Jul 2015 15:39:56 +0000 Received: by wgqq4 with SMTP id q4so66681616wgq.1 for ; Thu, 02 Jul 2015 08:39:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OSYE2d4AKz638YPeDjSxyeXLJRbOxTwzQ2Z+povCfBM=; b=cIGAgazf12bA6zI3a6AsHNLQp0mjw1T+Rb3uqHVLxukEf4Ld+t1PivAAixXmgareLm bAI+i0oX8nUM19fxkZUM1JxtxXYZW60phVfW8U52/w5HiaDKyotGl+1CEUDzaYNdMOF9 hA7ixjLAAmJPU0/a6aa1wZ8fnEGvIPnMKUk/Imn66OLiGvY5QvfWg9//Ea7kzPKPFNFx 5zgexFLFtTrQfcEhWUK7jfFOPPyZ1eWElBZkOsjiSVfk+1su6SM7Sev/w868RxgZftmB 0Rz/N/+4AHcFkNweRRftyYHGgq1rrvAb8ng8gMlN3nnDLs+VVj9fSB1oymQK864Glmti eW0w== X-Gm-Message-State: ALoCoQleCKRiZVnCE+gWL9QtAbPut0M9rVzwxbZi4Ui1xyJMXeKDxJ+TeZA7mBnGz+Ul6nGyo/sY X-Received: by 10.194.87.4 with SMTP id t4mr63995823wjz.84.1435851592085; Thu, 02 Jul 2015 08:39:52 -0700 (PDT) Received: from sale.linaroharston ([81.128.185.34]) by mx.google.com with ESMTPSA id fa8sm9223375wib.14.2015.07.02.08.39.50 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Jul 2015 08:39:51 -0700 (PDT) From: Charles Baylis To: Ramana.Radhakrishnan@arm.com, kyrylo.tkachov@arm.com Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 2/3] [ARM] PR63870 NEON error messages Date: Thu, 2 Jul 2015 16:39:43 +0100 Message-Id: <1435851584-16430-3-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1435851584-16430-1-git-send-email-charles.baylis@linaro.org> References: <1435851584-16430-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes gcc/ChangeLog: Charles Baylis * config/arm/arm-builtins.c: (arm_load1_qualifiers) Use qualifier_struct_load_store_lane_index. (arm_storestruct_lane_qualifiers) Likewise. * config/arm/neon.md: (neon_vld1_lane) Reverse lane numbers for big-endian. (neon_vst1_lane) Likewise. (neon_vld2_lane) Likewise. (neon_vst2_lane) Likewise. (neon_vld3_lane) Likewise. (neon_vst3_lane) Likewise. (neon_vld4_lane) Likewise. (neon_vst4_lane) Likewise. Change-Id: Ic39898d288701bc5b712490265be688f5620c4e2 --- gcc/config/arm/arm-builtins.c | 4 ++-- gcc/config/arm/neon.md | 49 +++++++++++++++++++++++-------------------- 2 files changed, 28 insertions(+), 25 deletions(-) diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 8f1253e..b7b7b12 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -145,7 +145,7 @@ arm_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_load1_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_const_pointer_map_mode, - qualifier_none, qualifier_immediate }; + qualifier_none, qualifier_struct_load_store_lane_index }; #define LOAD1LANE_QUALIFIERS (arm_load1_lane_qualifiers) /* The first argument (return type) of a store should be void type, @@ -164,7 +164,7 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer_map_mode, - qualifier_none, qualifier_immediate }; + qualifier_none, qualifier_struct_load_store_lane_index }; #define STORE1LANE_QUALIFIERS (arm_storestruct_lane_qualifiers) #define v8qi_UP V8QImode diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 654d9d5..dbd5852 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -4277,8 +4277,9 @@ UNSPEC_VLD1_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[3])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + operands[3] = GEN_INT (lane); if (lane < 0 || lane >= max) error ("lane out of range"); if (max == 1) @@ -4297,8 +4298,9 @@ UNSPEC_VLD1_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[3])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + operands[3] = GEN_INT (lane); int regno = REGNO (operands[0]); if (lane < 0 || lane >= max) error ("lane out of range"); @@ -4383,8 +4385,9 @@ UNSPEC_VST1_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[2])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); + operands[2] = GEN_INT (lane); if (lane < 0 || lane >= max) error ("lane out of range"); if (max == 1) @@ -4403,7 +4406,7 @@ UNSPEC_VST1_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[2])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[1]); if (lane < 0 || lane >= max) @@ -4412,8 +4415,8 @@ { lane -= max / 2; regno += 2; - operands[2] = GEN_INT (lane); } + operands[2] = GEN_INT (lane); operands[1] = gen_rtx_REG (mode, regno); if (max == 2) return "vst1.\t{%P1}, %A0"; @@ -4473,7 +4476,7 @@ UNSPEC_VLD2_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[3])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[0]); rtx ops[4]; @@ -4482,7 +4485,7 @@ ops[0] = gen_rtx_REG (DImode, regno); ops[1] = gen_rtx_REG (DImode, regno + 2); ops[2] = operands[1]; - ops[3] = operands[3]; + ops[3] = GEN_INT (lane); output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, %A2", ops); return ""; } @@ -4498,7 +4501,7 @@ UNSPEC_VLD2_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[3])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[0]); rtx ops[4]; @@ -4588,7 +4591,7 @@ UNSPEC_VST2_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[2])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[1]); rtx ops[4]; @@ -4597,7 +4600,7 @@ ops[0] = operands[0]; ops[1] = gen_rtx_REG (DImode, regno); ops[2] = gen_rtx_REG (DImode, regno + 2); - ops[3] = operands[2]; + ops[3] = GEN_INT (lane); output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, %A0", ops); return ""; } @@ -4613,7 +4616,7 @@ UNSPEC_VST2_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[2])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[1]); rtx ops[4]; @@ -4732,7 +4735,7 @@ UNSPEC_VLD3_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT lane = ENDIAN_LANE_N (mode, INTVAL (operands[3])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[0]); rtx ops[5]; @@ -4742,7 +4745,7 @@ ops[1] = gen_rtx_REG (DImode, regno + 2); ops[2] = gen_rtx_REG (DImode, regno + 4); ops[3] = operands[1]; - ops[4] = operands[3]; + ops[4] = GEN_INT (lane); output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3", ops); return ""; @@ -4759,7 +4762,7 @@ UNSPEC_VLD3_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[3])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[0]); rtx ops[5]; @@ -4904,7 +4907,7 @@ UNSPEC_VST3_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[2])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[1]); rtx ops[5]; @@ -4914,7 +4917,7 @@ ops[1] = gen_rtx_REG (DImode, regno); ops[2] = gen_rtx_REG (DImode, regno + 2); ops[3] = gen_rtx_REG (DImode, regno + 4); - ops[4] = operands[2]; + ops[4] = GEN_INT (lane); output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0", ops); return ""; @@ -4931,7 +4934,7 @@ UNSPEC_VST3_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[2])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[1]); rtx ops[5]; @@ -5054,7 +5057,7 @@ UNSPEC_VLD4_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[3])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[0]); rtx ops[6]; @@ -5065,7 +5068,7 @@ ops[2] = gen_rtx_REG (DImode, regno + 4); ops[3] = gen_rtx_REG (DImode, regno + 6); ops[4] = operands[1]; - ops[5] = operands[3]; + ops[5] = GEN_INT (lane); output_asm_insn ("vld4.\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4", ops); return ""; @@ -5082,7 +5085,7 @@ UNSPEC_VLD4_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[3]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[3])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[0]); rtx ops[6]; @@ -5234,7 +5237,7 @@ UNSPEC_VST4_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[2])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[1]); rtx ops[6]; @@ -5245,7 +5248,7 @@ ops[2] = gen_rtx_REG (DImode, regno + 2); ops[3] = gen_rtx_REG (DImode, regno + 4); ops[4] = gen_rtx_REG (DImode, regno + 6); - ops[5] = operands[2]; + ops[5] = GEN_INT (lane); output_asm_insn ("vst4.\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0", ops); return ""; @@ -5262,7 +5265,7 @@ UNSPEC_VST4_LANE))] "TARGET_NEON" { - HOST_WIDE_INT lane = INTVAL (operands[2]); + HOST_WIDE_INT lane = ENDIAN_LANE_N(mode, INTVAL (operands[2])); HOST_WIDE_INT max = GET_MODE_NUNITS (mode); int regno = REGNO (operands[1]); rtx ops[6];