diff mbox

[[ARM/AArch64,testsuite] 04/36] Add vld1_lane tests.

Message ID 1421162314-25779-5-git-send-email-christophe.lyon@linaro.org
State New
Headers show

Commit Message

Christophe Lyon Jan. 13, 2015, 3:18 p.m. UTC 
* gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.

Comments

Tejas Belagod Jan. 16, 2015, 2:09 p.m. UTC | #1 
On 13/01/15 15:18, Christophe Lyon wrote:
> 	* gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
> new file mode 100644
> index 0000000..168cf5e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
> @@ -0,0 +1,129 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> +				       0xaa, 0xaa, 0xf0, 0xaa };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> +					0xaa, 0xaa, 0xaa, 0xf0 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> +					0xaa, 0xaa, 0xaa, 0xf0 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xaaaaaaaa, 0xc1800000 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> +					0xaa, 0xaa, 0xaa, 0xaa,
> +					0xaa, 0xaa, 0xaa, 0xaa,
> +					0xaa, 0xaa, 0xaa, 0xf0 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
> +					0xaaaa, 0xfff0, 0xaaaa, 0xaaaa };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
> +					0xfffffff0, 0xaaaaaaaa };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
> +					0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> +					 0xaa, 0xaa, 0xaa, 0xaa,
> +					 0xaa, 0xaa, 0xaa, 0xaa,
> +					 0xf0, 0xaa, 0xaa, 0xaa };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
> +					 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
> +					 0xfffffff0, 0xaaaaaaaa };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
> +					 0xaaaaaaaaaaaaaaaa };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> +					 0xaa, 0xaa, 0xaa, 0xaa,
> +					 0xaa, 0xaa, 0xaa, 0xaa,
> +					 0xf0, 0xaa, 0xaa, 0xaa };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
> +					 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
> +					   0xc1800000, 0xaaaaaaaa };
> +
> +#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
> +void exec_vld1_lane (void)
> +{
> +  /* Fill vector_src with 0xAA, then load 1 lane.  */
> +#define TEST_VLD1_LANE(Q, T1, T2, W, N, L)				\
> +  memset (VECT_VAR(buffer_src, T1, W, N), 0xAA, W/8*N);			\
> +  VECT_VAR(vector_src, T1, W, N) =					\
> +    vld1##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N));			\
> +  VECT_VAR(vector, T1, W, N) =						\
> +    vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N),			\
> +			   VECT_VAR(vector_src, T1, W, N), L);		\
> +  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector, T1, W, N))
> +
> +  DECL_VARIABLE_ALL_VARIANTS(vector);
> +  DECL_VARIABLE_ALL_VARIANTS(vector_src);
> +
> +  ARRAY(buffer_src, int, 8, 8);
> +  ARRAY(buffer_src, int, 16, 4);
> +  ARRAY(buffer_src, int, 32, 2);
> +  ARRAY(buffer_src, int, 64, 1);
> +  ARRAY(buffer_src, uint, 8, 8);
> +  ARRAY(buffer_src, uint, 16, 4);
> +  ARRAY(buffer_src, uint, 32, 2);
> +  ARRAY(buffer_src, uint, 64, 1);
> +  ARRAY(buffer_src, poly, 8, 8);
> +  ARRAY(buffer_src, poly, 16, 4);
> +  ARRAY(buffer_src, float, 32, 2);
> +
> +  ARRAY(buffer_src, int, 8, 16);
> +  ARRAY(buffer_src, int, 16, 8);
> +  ARRAY(buffer_src, int, 32, 4);
> +  ARRAY(buffer_src, int, 64, 2);
> +  ARRAY(buffer_src, uint, 8, 16);
> +  ARRAY(buffer_src, uint, 16, 8);
> +  ARRAY(buffer_src, uint, 32, 4);
> +  ARRAY(buffer_src, uint, 64, 2);
> +  ARRAY(buffer_src, poly, 8, 16);
> +  ARRAY(buffer_src, poly, 16, 8);
> +  ARRAY(buffer_src, float, 32, 4);
> +
> +  clean_results ();
> +
> +  /* Choose lane arbitrarily.  */
> +  TEST_VLD1_LANE(, int, s, 8, 8, 6);
> +  TEST_VLD1_LANE(, int, s, 16, 4, 3);
> +  TEST_VLD1_LANE(, int, s, 32, 2, 1);
> +  TEST_VLD1_LANE(, int, s, 64, 1, 0);
> +  TEST_VLD1_LANE(, uint, u, 8, 8, 7);
> +  TEST_VLD1_LANE(, uint, u, 16, 4, 3);
> +  TEST_VLD1_LANE(, uint, u, 32, 2, 1);
> +  TEST_VLD1_LANE(, uint, u, 64, 1, 0);
> +  TEST_VLD1_LANE(, poly, p, 8, 8, 7);
> +  TEST_VLD1_LANE(, poly, p, 16, 4, 3);
> +  TEST_VLD1_LANE(, float, f, 32, 2, 1);
> +
> +  TEST_VLD1_LANE(q, int, s, 8, 16, 15);
> +  TEST_VLD1_LANE(q, int, s, 16, 8, 5);
> +  TEST_VLD1_LANE(q, int, s, 32, 4, 2);
> +  TEST_VLD1_LANE(q, int, s, 64, 2, 1);
> +  TEST_VLD1_LANE(q, uint, u, 8, 16, 12);
> +  TEST_VLD1_LANE(q, uint, u, 16, 8, 6);
> +  TEST_VLD1_LANE(q, uint, u, 32, 4, 2);
> +  TEST_VLD1_LANE(q, uint, u, 64, 2, 0);
> +  TEST_VLD1_LANE(q, poly, p, 8, 16, 12);
> +  TEST_VLD1_LANE(q, poly, p, 16, 8, 6);
> +  TEST_VLD1_LANE(q, float, f, 32, 4, 2);
> +

Hmm.. again, I don't see vld1<q>_lane_f64?

> +#ifndef __CC_ARM
> +  /* Check runtime assertions. With RVCT, the check is performed at
> +     compile-time */
> +  //  TEST_VLD1_LANE(, int, s, 64, 1, 1);
> +#endif
> +

Does this belong in this patch?

Otherwise, it looks good to me(I cannot approve though).

Thanks,
Tejas.
Christophe Lyon Jan. 16, 2015, 4:23 p.m. UTC | #2 
On 16 January 2015 at 15:09, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>>         * gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
>>
>> diff --git
>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
>> new file mode 100644
>> index 0000000..168cf5e
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
>> @@ -0,0 +1,129 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results.  */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> +                                      0xaa, 0xaa, 0xf0, 0xaa };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> +                                       0xaa, 0xaa, 0xaa, 0xf0 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> +                                       0xaa, 0xaa, 0xaa, 0xf0 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0
>> };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xaaaaaaaa, 0xc1800000 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> +                                       0xaa, 0xaa, 0xaa, 0xaa,
>> +                                       0xaa, 0xaa, 0xaa, 0xaa,
>> +                                       0xaa, 0xaa, 0xaa, 0xf0 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
>> +                                       0xaaaa, 0xfff0, 0xaaaa, 0xaaaa };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
>> +                                       0xfffffff0, 0xaaaaaaaa };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
>> +                                       0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> +                                        0xaa, 0xaa, 0xaa, 0xaa,
>> +                                        0xaa, 0xaa, 0xaa, 0xaa,
>> +                                        0xf0, 0xaa, 0xaa, 0xaa };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
>> +                                        0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
>> +                                        0xfffffff0, 0xaaaaaaaa };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
>> +                                        0xaaaaaaaaaaaaaaaa };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> +                                        0xaa, 0xaa, 0xaa, 0xaa,
>> +                                        0xaa, 0xaa, 0xaa, 0xaa,
>> +                                        0xf0, 0xaa, 0xaa, 0xaa };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
>> +                                        0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
>> +                                          0xc1800000, 0xaaaaaaaa };
>> +
>> +#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
>> +void exec_vld1_lane (void)
>> +{
>> +  /* Fill vector_src with 0xAA, then load 1 lane.  */
>> +#define TEST_VLD1_LANE(Q, T1, T2, W, N, L)                             \
>> +  memset (VECT_VAR(buffer_src, T1, W, N), 0xAA, W/8*N);
>> \
>> +  VECT_VAR(vector_src, T1, W, N) =                                     \
>> +    vld1##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N));                 \
>> +  VECT_VAR(vector, T1, W, N) =                                         \
>> +    vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N),                 \
>> +                          VECT_VAR(vector_src, T1, W, N), L);          \
>> +  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector, T1, W,
>> N))
>> +
>> +  DECL_VARIABLE_ALL_VARIANTS(vector);
>> +  DECL_VARIABLE_ALL_VARIANTS(vector_src);
>> +
>> +  ARRAY(buffer_src, int, 8, 8);
>> +  ARRAY(buffer_src, int, 16, 4);
>> +  ARRAY(buffer_src, int, 32, 2);
>> +  ARRAY(buffer_src, int, 64, 1);
>> +  ARRAY(buffer_src, uint, 8, 8);
>> +  ARRAY(buffer_src, uint, 16, 4);
>> +  ARRAY(buffer_src, uint, 32, 2);
>> +  ARRAY(buffer_src, uint, 64, 1);
>> +  ARRAY(buffer_src, poly, 8, 8);
>> +  ARRAY(buffer_src, poly, 16, 4);
>> +  ARRAY(buffer_src, float, 32, 2);
>> +
>> +  ARRAY(buffer_src, int, 8, 16);
>> +  ARRAY(buffer_src, int, 16, 8);
>> +  ARRAY(buffer_src, int, 32, 4);
>> +  ARRAY(buffer_src, int, 64, 2);
>> +  ARRAY(buffer_src, uint, 8, 16);
>> +  ARRAY(buffer_src, uint, 16, 8);
>> +  ARRAY(buffer_src, uint, 32, 4);
>> +  ARRAY(buffer_src, uint, 64, 2);
>> +  ARRAY(buffer_src, poly, 8, 16);
>> +  ARRAY(buffer_src, poly, 16, 8);
>> +  ARRAY(buffer_src, float, 32, 4);
>> +
>> +  clean_results ();
>> +
>> +  /* Choose lane arbitrarily.  */
>> +  TEST_VLD1_LANE(, int, s, 8, 8, 6);
>> +  TEST_VLD1_LANE(, int, s, 16, 4, 3);
>> +  TEST_VLD1_LANE(, int, s, 32, 2, 1);
>> +  TEST_VLD1_LANE(, int, s, 64, 1, 0);
>> +  TEST_VLD1_LANE(, uint, u, 8, 8, 7);
>> +  TEST_VLD1_LANE(, uint, u, 16, 4, 3);
>> +  TEST_VLD1_LANE(, uint, u, 32, 2, 1);
>> +  TEST_VLD1_LANE(, uint, u, 64, 1, 0);
>> +  TEST_VLD1_LANE(, poly, p, 8, 8, 7);
>> +  TEST_VLD1_LANE(, poly, p, 16, 4, 3);
>> +  TEST_VLD1_LANE(, float, f, 32, 2, 1);
>> +
>> +  TEST_VLD1_LANE(q, int, s, 8, 16, 15);
>> +  TEST_VLD1_LANE(q, int, s, 16, 8, 5);
>> +  TEST_VLD1_LANE(q, int, s, 32, 4, 2);
>> +  TEST_VLD1_LANE(q, int, s, 64, 2, 1);
>> +  TEST_VLD1_LANE(q, uint, u, 8, 16, 12);
>> +  TEST_VLD1_LANE(q, uint, u, 16, 8, 6);
>> +  TEST_VLD1_LANE(q, uint, u, 32, 4, 2);
>> +  TEST_VLD1_LANE(q, uint, u, 64, 2, 0);
>> +  TEST_VLD1_LANE(q, poly, p, 8, 16, 12);
>> +  TEST_VLD1_LANE(q, poly, p, 16, 8, 6);
>> +  TEST_VLD1_LANE(q, float, f, 32, 4, 2);
>> +
>
>
> Hmm.. again, I don't see vld1<q>_lane_f64?

Same answer: unless I am mistaken it isn't supported on armv7, and
indeed the tests need to be expanded.

>> +#ifndef __CC_ARM
>> +  /* Check runtime assertions. With RVCT, the check is performed at
>> +     compile-time */
>> +  //  TEST_VLD1_LANE(, int, s, 64, 1, 1);
>> +#endif
>> +
>
> Does this belong in this patch?
Good catch!
The original testsuite uses RVCT features not present in GCC, and I
forgot to remove this chunk.

> Otherwise, it looks good to me(I cannot approve though).
>
> Thanks,
> Tejas.
>
Marcus Shawcroft Jan. 16, 2015, 5:17 p.m. UTC | #3 
On 16 January 2015 at 16:23, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 15:09, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>>
>>>         * gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.



>> Hmm.. again, I don't see vld1<q>_lane_f64?
>
> Same answer: unless I am mistaken it isn't supported on armv7, and
> indeed the tests need to be expanded.
>
>>> +#ifndef __CC_ARM
>>> +  /* Check runtime assertions. With RVCT, the check is performed at
>>> +     compile-time */
>>> +  //  TEST_VLD1_LANE(, int, s, 64, 1, 1);
>>> +#endif
>>> +
>>
>> Does this belong in this patch?
> Good catch!
> The original testsuite uses RVCT features not present in GCC, and I
> forgot to remove this chunk.
>
>> Otherwise, it looks good to me(I cannot approve though).


OK with that hunk dropped, provided no new fails on aarch64[_be] and arm.
/Marcus
diff mbox

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
new file mode 100644
index 0000000..168cf5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
@@ -0,0 +1,129 @@ 
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+				       0xaa, 0xaa, 0xf0, 0xaa };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+					0xaa, 0xaa, 0xaa, 0xf0 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+					0xaa, 0xaa, 0xaa, 0xf0 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xaaaaaaaa, 0xc1800000 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+					0xaa, 0xaa, 0xaa, 0xaa,
+					0xaa, 0xaa, 0xaa, 0xaa,
+					0xaa, 0xaa, 0xaa, 0xf0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
+					0xaaaa, 0xfff0, 0xaaaa, 0xaaaa };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
+					0xfffffff0, 0xaaaaaaaa };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
+					0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+					 0xaa, 0xaa, 0xaa, 0xaa,
+					 0xaa, 0xaa, 0xaa, 0xaa,
+					 0xf0, 0xaa, 0xaa, 0xaa };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
+					 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
+					 0xfffffff0, 0xaaaaaaaa };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
+					 0xaaaaaaaaaaaaaaaa };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+					 0xaa, 0xaa, 0xaa, 0xaa,
+					 0xaa, 0xaa, 0xaa, 0xaa,
+					 0xf0, 0xaa, 0xaa, 0xaa };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
+					 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
+					   0xc1800000, 0xaaaaaaaa };
+
+#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
+void exec_vld1_lane (void)
+{
+  /* Fill vector_src with 0xAA, then load 1 lane.  */
+#define TEST_VLD1_LANE(Q, T1, T2, W, N, L)				\
+  memset (VECT_VAR(buffer_src, T1, W, N), 0xAA, W/8*N);			\
+  VECT_VAR(vector_src, T1, W, N) =					\
+    vld1##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N));			\
+  VECT_VAR(vector, T1, W, N) =						\
+    vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N),			\
+			   VECT_VAR(vector_src, T1, W, N), L);		\
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector, T1, W, N))
+
+  DECL_VARIABLE_ALL_VARIANTS(vector);
+  DECL_VARIABLE_ALL_VARIANTS(vector_src);
+
+  ARRAY(buffer_src, int, 8, 8);
+  ARRAY(buffer_src, int, 16, 4);
+  ARRAY(buffer_src, int, 32, 2);
+  ARRAY(buffer_src, int, 64, 1);
+  ARRAY(buffer_src, uint, 8, 8);
+  ARRAY(buffer_src, uint, 16, 4);
+  ARRAY(buffer_src, uint, 32, 2);
+  ARRAY(buffer_src, uint, 64, 1);
+  ARRAY(buffer_src, poly, 8, 8);
+  ARRAY(buffer_src, poly, 16, 4);
+  ARRAY(buffer_src, float, 32, 2);
+
+  ARRAY(buffer_src, int, 8, 16);
+  ARRAY(buffer_src, int, 16, 8);
+  ARRAY(buffer_src, int, 32, 4);
+  ARRAY(buffer_src, int, 64, 2);
+  ARRAY(buffer_src, uint, 8, 16);
+  ARRAY(buffer_src, uint, 16, 8);
+  ARRAY(buffer_src, uint, 32, 4);
+  ARRAY(buffer_src, uint, 64, 2);
+  ARRAY(buffer_src, poly, 8, 16);
+  ARRAY(buffer_src, poly, 16, 8);
+  ARRAY(buffer_src, float, 32, 4);
+
+  clean_results ();
+
+  /* Choose lane arbitrarily.  */
+  TEST_VLD1_LANE(, int, s, 8, 8, 6);
+  TEST_VLD1_LANE(, int, s, 16, 4, 3);
+  TEST_VLD1_LANE(, int, s, 32, 2, 1);
+  TEST_VLD1_LANE(, int, s, 64, 1, 0);
+  TEST_VLD1_LANE(, uint, u, 8, 8, 7);
+  TEST_VLD1_LANE(, uint, u, 16, 4, 3);
+  TEST_VLD1_LANE(, uint, u, 32, 2, 1);
+  TEST_VLD1_LANE(, uint, u, 64, 1, 0);
+  TEST_VLD1_LANE(, poly, p, 8, 8, 7);
+  TEST_VLD1_LANE(, poly, p, 16, 4, 3);
+  TEST_VLD1_LANE(, float, f, 32, 2, 1);
+
+  TEST_VLD1_LANE(q, int, s, 8, 16, 15);
+  TEST_VLD1_LANE(q, int, s, 16, 8, 5);
+  TEST_VLD1_LANE(q, int, s, 32, 4, 2);
+  TEST_VLD1_LANE(q, int, s, 64, 2, 1);
+  TEST_VLD1_LANE(q, uint, u, 8, 16, 12);
+  TEST_VLD1_LANE(q, uint, u, 16, 8, 6);
+  TEST_VLD1_LANE(q, uint, u, 32, 4, 2);
+  TEST_VLD1_LANE(q, uint, u, 64, 2, 0);
+  TEST_VLD1_LANE(q, poly, p, 8, 16, 12);
+  TEST_VLD1_LANE(q, poly, p, 16, 8, 6);
+  TEST_VLD1_LANE(q, float, f, 32, 4, 2);
+
+#ifndef __CC_ARM
+  /* Check runtime assertions. With RVCT, the check is performed at
+     compile-time */
+  //  TEST_VLD1_LANE(, int, s, 64, 1, 1);
+#endif
+
+  CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+  exec_vld1_lane ();
+  return 0;
+}