From patchwork Tue Jan 13 15:18:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 428453 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C6549140161 for ; Wed, 14 Jan 2015 02:24:26 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=IlzBD3Z8DideMTwERBCKd2hZjKJh6++zyQpGqt40A+NEXcgE7wxKv 6mQOu0albGc2k1IdfIxokDx14Q9nnNDQAi8T7SI8DYep+zT18N2Xb2ojHWiRIqzY lAyEfoTR9GEVN1agbWwb2hV+6UR33EWzzgkbfbw5EPJxf2PaetmJ5Y= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; s=default; bh=XHfxgV9PLqUqANAnis1aPk/b0xU=; b=CezqMJinu5YA8b4iUzkOXIf9saav VRtMfCgixELNw2khAhJxVEKWSEpUCGlPX3FxCc5X7aEtXtJjgjATFwxPRvlb5p/P zB/olm4jK02DyIvgYrIqBacgaMw0ntgqyhhD3j7OLhcJUyMVZSjhFJLhkVHW5GnA UcIr6A47VtUGkAQ= Received: (qmail 25393 invoked by alias); 13 Jan 2015 15:19:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 23700 invoked by uid 89); 13 Jan 2015 15:19:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f173.google.com Received: from mail-wi0-f173.google.com (HELO mail-wi0-f173.google.com) (209.85.212.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 13 Jan 2015 15:19:14 +0000 Received: by mail-wi0-f173.google.com with SMTP id em10so6194167wid.0 for ; Tue, 13 Jan 2015 07:19:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=lhk31MIaRiADpHjGmbSrcTy/O65uSf1qWAn+JHRrArI=; b=U4omN5k0Ks+WELWX9sGo2s3WAyYAAexAL+CEzvb8LM8yHsWLdvXQl9nvtt8Z7sxZlw BaYNQNEtPgyct2VLsYfEOqjND9801GrKjPeWeMrxbmNxQsgFx2JC1qyGx/sVAI/iTjc9 NMX431X08ijnhaILzXtA6ykZAOH+sp9e6Ylw4m9frLxJiGgb4Dbq1LfX2UNeHVim/2Fk eyxC5OKAib0kJVT5UxxnFg1g3Vtt7cxYLPvEbHyYm9fo5sAbFjSnjF6uemKwjpaWcGhF bFU3yw5gJRGbhIIOgW7CSlLdbVHAWBBjb31sc/l4vEx8l0bOLWYJ5EGvSDrxn8I42dVl cVLA== X-Gm-Message-State: ALoCoQkgEswMfYl2NFqICHIAe3F0OG8A888kDtmoYrPhssQG8T0pBQJA15NMNQ9RU37DCpGErx0t X-Received: by 10.194.2.75 with SMTP id 11mr17540425wjs.78.1421162351098; Tue, 13 Jan 2015 07:19:11 -0800 (PST) Received: from babel.clyon.hd.free.fr (vig38-2-82-225-222-175.fbx.proxad.net. [82.225.222.175]) by mx.google.com with ESMTPSA id jr4sm26100313wjc.20.2015.01.13.07.19.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Jan 2015 07:19:10 -0800 (PST) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc. Date: Tue, 13 Jan 2015 16:18:17 +0100 Message-Id: <1421162314-25779-20-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> X-IsSubscribed: yes * gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vsubl.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Use code from vXXXl.inc. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc new file mode 100644 index 0000000..bd4c8fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc @@ -0,0 +1,70 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* Basic test: y=vaddl(x1,x2), then store the result. */ +#define TEST_VADDL1(INSN, T1, T2, W, W2, N) \ + VECT_VAR(vector_res, T1, W2, N) = \ + INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector2, T1, W, N)); \ + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N)) + +#define TEST_VADDL(INSN, T1, T2, W, W2, N) \ + TEST_VADDL1(INSN, T1, T2, W, W2, N) + + DECL_VARIABLE(vector, int, 8, 8); + DECL_VARIABLE(vector, int, 16, 4); + DECL_VARIABLE(vector, int, 32, 2); + DECL_VARIABLE(vector, uint, 8, 8); + DECL_VARIABLE(vector, uint, 16, 4); + DECL_VARIABLE(vector, uint, 32, 2); + + DECL_VARIABLE(vector2, int, 8, 8); + DECL_VARIABLE(vector2, int, 16, 4); + DECL_VARIABLE(vector2, int, 32, 2); + DECL_VARIABLE(vector2, uint, 8, 8); + DECL_VARIABLE(vector2, uint, 16, 4); + DECL_VARIABLE(vector2, uint, 32, 2); + + DECL_VARIABLE(vector_res, int, 16, 8); + DECL_VARIABLE(vector_res, int, 32, 4); + DECL_VARIABLE(vector_res, int, 64, 2); + DECL_VARIABLE(vector_res, uint, 16, 8); + DECL_VARIABLE(vector_res, uint, 32, 4); + DECL_VARIABLE(vector_res, uint, 64, 2); + + clean_results (); + + /* Initialize input "vector" from "buffer". */ + VLOAD(vector, buffer, , int, s, 8, 8); + VLOAD(vector, buffer, , int, s, 16, 4); + VLOAD(vector, buffer, , int, s, 32, 2); + VLOAD(vector, buffer, , uint, u, 8, 8); + VLOAD(vector, buffer, , uint, u, 16, 4); + VLOAD(vector, buffer, , uint, u, 32, 2); + + /* Choose init value arbitrarily. */ + VDUP(vector2, , int, s, 8, 8, -13); + VDUP(vector2, , int, s, 16, 4, -14); + VDUP(vector2, , int, s, 32, 2, -16); + VDUP(vector2, , uint, u, 8, 8, 0xf3); + VDUP(vector2, , uint, u, 16, 4, 0xfff1); + VDUP(vector2, , uint, u, 32, 2, 0xfffffff0); + + /* Execute the tests. */ + TEST_VADDL(INSN_NAME, int, s, 8, 16, 8); + TEST_VADDL(INSN_NAME, int, s, 16, 32, 4); + TEST_VADDL(INSN_NAME, int, s, 32, 64, 2); + TEST_VADDL(INSN_NAME, uint, u, 8, 16, 8); + TEST_VADDL(INSN_NAME, uint, u, 16, 32, 4); + TEST_VADDL(INSN_NAME, uint, u, 32, 64, 2); + + CHECK_RESULTS (TEST_MSG, ""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c index 030785d..020d9f8 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c @@ -2,6 +2,9 @@ #include "arm-neon-ref.h" #include "compute-ref-data.h" +#define INSN_NAME vaddl +#define TEST_MSG "VADDL" + /* Expected results. */ VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33 }; @@ -45,76 +48,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, 0x33333333, 0x33333333 }; -#define INSN_NAME vaddl -#define TEST_MSG "VADDL" - -#define FNNAME1(NAME) exec_ ## NAME -#define FNNAME(NAME) FNNAME1(NAME) - -void FNNAME (INSN_NAME) (void) -{ - /* Basic test: y=vaddl(x1,x2), then store the result. */ -#define TEST_VADDL1(INSN, T1, T2, W, W2, N) \ - VECT_VAR(vector_res, T1, W2, N) = \ - INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \ - VECT_VAR(vector2, T1, W, N)); \ - vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N)) - -#define TEST_VADDL(INSN, T1, T2, W, W2, N) \ - TEST_VADDL1(INSN, T1, T2, W, W2, N) - - DECL_VARIABLE(vector, int, 8, 8); - DECL_VARIABLE(vector, int, 16, 4); - DECL_VARIABLE(vector, int, 32, 2); - DECL_VARIABLE(vector, uint, 8, 8); - DECL_VARIABLE(vector, uint, 16, 4); - DECL_VARIABLE(vector, uint, 32, 2); - - DECL_VARIABLE(vector2, int, 8, 8); - DECL_VARIABLE(vector2, int, 16, 4); - DECL_VARIABLE(vector2, int, 32, 2); - DECL_VARIABLE(vector2, uint, 8, 8); - DECL_VARIABLE(vector2, uint, 16, 4); - DECL_VARIABLE(vector2, uint, 32, 2); - - DECL_VARIABLE(vector_res, int, 16, 8); - DECL_VARIABLE(vector_res, int, 32, 4); - DECL_VARIABLE(vector_res, int, 64, 2); - DECL_VARIABLE(vector_res, uint, 16, 8); - DECL_VARIABLE(vector_res, uint, 32, 4); - DECL_VARIABLE(vector_res, uint, 64, 2); - - clean_results (); - - /* Initialize input "vector" from "buffer". */ - VLOAD(vector, buffer, , int, s, 8, 8); - VLOAD(vector, buffer, , int, s, 16, 4); - VLOAD(vector, buffer, , int, s, 32, 2); - VLOAD(vector, buffer, , uint, u, 8, 8); - VLOAD(vector, buffer, , uint, u, 16, 4); - VLOAD(vector, buffer, , uint, u, 32, 2); - - /* Choose init value arbitrarily. */ - VDUP(vector2, , int, s, 8, 8, -13); - VDUP(vector2, , int, s, 16, 4, -14); - VDUP(vector2, , int, s, 32, 2, -16); - VDUP(vector2, , uint, u, 8, 8, 0xf3); - VDUP(vector2, , uint, u, 16, 4, 0xfff1); - VDUP(vector2, , uint, u, 32, 2, 0xfffffff0); - - /* Execute the tests. */ - TEST_VADDL(INSN_NAME, int, s, 8, 16, 8); - TEST_VADDL(INSN_NAME, int, s, 16, 32, 4); - TEST_VADDL(INSN_NAME, int, s, 32, 64, 2); - TEST_VADDL(INSN_NAME, uint, u, 8, 16, 8); - TEST_VADDL(INSN_NAME, uint, u, 16, 32, 4); - TEST_VADDL(INSN_NAME, uint, u, 32, 64, 2); - - CHECK_RESULTS (TEST_MSG, ""); -} - -int main (void) -{ - FNNAME (INSN_NAME) (); - return 0; -} +#include "vXXXl.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c new file mode 100644 index 0000000..b765b2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c @@ -0,0 +1,48 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vsubl +#define TEST_MSG "VSUBL" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0, + 0x1, 0x2, 0x3, 0x4 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0, + 0x1, 0x2, 0x3, 0x4 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0x0, 0x1, 0x2 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x0, 0x1 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +#include "vXXXl.inc"