[1/2,AArch64] Core definition for APM XGene-1 and associated cost-table.

To keep this change separately buildable from the pipeline model,
this patch directs the APM XGene-1 to use the generic scheduling
model.
---
 gcc/ChangeLog                        |   7 +++
 gcc/config/aarch64/aarch64-cores.def |   1 +
 gcc/config/aarch64/aarch64-tune.md   |   2 +-
 gcc/config/aarch64/aarch64.c         |  62 +++++++++++++++++++++
 gcc/config/arm/aarch-cost-tables.h   | 101 +++++++++++++++++++++++++++++++++++
 5 files changed, 172 insertions(+), 1 deletion(-)

Hi Philipp,

The new -mcpu option needs documenting in invoke.texi and a note to 
wwwdocs in changes.html would be nice too.

Kyrill

On 19/11/14 17:32, Philipp Tomsich wrote:
> To keep this change separately buildable from the pipeline model,
> this patch directs the APM XGene-1 to use the generic scheduling
> model.
> ---
>   gcc/ChangeLog                        |   7 +++
>   gcc/config/aarch64/aarch64-cores.def |   1 +
>   gcc/config/aarch64/aarch64-tune.md   |   2 +-
>   gcc/config/aarch64/aarch64.c         |  62 +++++++++++++++++++++
>   gcc/config/arm/aarch-cost-tables.h   | 101 +++++++++++++++++++++++++++++++++++
>   5 files changed, 172 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index 2fa58ca..5b389c5 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,10 @@
> +2014-11-19  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
> +
> +	* config/aarch64/aarch64-cores.def (xgene1): Update/add the
> +	xgene1 (APM XGene-1) core definition.
> +	* gcc/config/aarch64/aarch64.c: Add cost tables for APM XGene-1
> +	* config/arm/aarch-cost-tables.h: Add cost tables for APM XGene-1
> +
>   2014-11-18  Maciej W. Rozycki  <macro@codesourcery.com>
>   
>   	* config/mips/mips.md (compression): Add `micromips32' setting.
> diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
> index 312941f..e553e50 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -37,6 +37,7 @@
>   AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC, cortexa53)
>   AARCH64_CORE("cortex-a57",  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC, cortexa57)
>   AARCH64_CORE("thunderx",    thunderx,  thunderx, 8,  AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx)
> +AARCH64_CORE("xgene1",      xgene1,    xgene1,    8,  AARCH64_FL_FPSIMD, xgene1)
>   
>   /* V8 big.LITTLE implementations.  */
>   
> diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
> index c717ea8..6409082 100644
> --- a/gcc/config/aarch64/aarch64-tune.md
> +++ b/gcc/config/aarch64/aarch64-tune.md
> @@ -1,5 +1,5 @@
>   ;; -*- buffer-read-only: t -*-
>   ;; Generated automatically by gentune.sh from aarch64-cores.def
>   (define_attr "tune"
> -	"cortexa53,cortexa15,thunderx,cortexa57cortexa53"
> +	"cortexa53,cortexa15,thunderx,xgene1,cortexa57cortexa53"
>   	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index 4fec21e..9b92527 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -226,6 +226,27 @@ static const struct cpu_addrcost_table cortexa57_addrcost_table =
>   #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
>   __extension__
>   #endif
> +static const struct cpu_addrcost_table xgene1_addrcost_table =
> +{
> +#if HAVE_DESIGNATED_INITIALIZERS
> +  .addr_scale_costs =
> +#endif
> +    {
> +      NAMED_PARAM (hi, 1),
> +      NAMED_PARAM (si, 0),
> +      NAMED_PARAM (di, 0),
> +      NAMED_PARAM (ti, 1),
> +    },
> +  NAMED_PARAM (pre_modify, 1),
> +  NAMED_PARAM (post_modify, 0),
> +  NAMED_PARAM (register_offset, 0),
> +  NAMED_PARAM (register_extend, 1),
> +  NAMED_PARAM (imm_offset, 0),
> +};
> +
> +#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
> +__extension__
> +#endif
>   static const struct cpu_regmove_cost generic_regmove_cost =
>   {
>     NAMED_PARAM (GP2GP, 1),
> @@ -262,6 +283,17 @@ static const struct cpu_regmove_cost thunderx_regmove_cost =
>     NAMED_PARAM (FP2FP, 4)
>   };
>   
> +static const struct cpu_regmove_cost xgene1_regmove_cost =
> +{
> +  NAMED_PARAM (GP2GP, 1),
> +  NAMED_PARAM (GP2FP, 8),
> +  NAMED_PARAM (FP2GP, 8),
> +  /* We currently do not provide direct support for TFmode Q->Q move.
> +     Therefore we need to raise the cost above 2 in order to have
> +     reload handle the situation.  */
> +  NAMED_PARAM (FP2FP, 4)
> +};
> +
>   /* Generic costs for vector insn classes.  */
>   #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
>   __extension__
> @@ -302,6 +334,26 @@ static const struct cpu_vector_cost cortexa57_vector_cost =
>     NAMED_PARAM (cond_not_taken_branch_cost, 1)
>   };
>   
> +/* Generic costs for vector insn classes.  */
> +#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
> +__extension__
> +#endif
> +static const struct cpu_vector_cost xgene1_vector_cost =
> +{
> +  NAMED_PARAM (scalar_stmt_cost, 1),
> +  NAMED_PARAM (scalar_load_cost, 5),
> +  NAMED_PARAM (scalar_store_cost, 1),
> +  NAMED_PARAM (vec_stmt_cost, 2),
> +  NAMED_PARAM (vec_to_scalar_cost, 4),
> +  NAMED_PARAM (scalar_to_vec_cost, 4),
> +  NAMED_PARAM (vec_align_load_cost, 10),
> +  NAMED_PARAM (vec_unalign_load_cost, 10),
> +  NAMED_PARAM (vec_unalign_store_cost, 2),
> +  NAMED_PARAM (vec_store_cost, 2),
> +  NAMED_PARAM (cond_taken_branch_cost, 2),
> +  NAMED_PARAM (cond_not_taken_branch_cost, 1)
> +};
> +
>   #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
>   __extension__
>   #endif
> @@ -345,6 +397,16 @@ static const struct tune_params thunderx_tunings =
>     NAMED_PARAM (issue_rate, 2)
>   };
>   
> +static const struct tune_params xgene1_tunings =
> +{
> +  &xgene1_extra_costs,
> +  &xgene1_addrcost_table,
> +  &xgene1_regmove_cost,
> +  &xgene1_vector_cost,
> +  NAMED_PARAM (memmov_cost, 4),
> +  NAMED_PARAM (issue_rate, 4)
> +};
> +
>   /* A processor implementing AArch64.  */
>   struct processor
>   {
> diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h
> index adf8708..a6313d6 100644
> --- a/gcc/config/arm/aarch-cost-tables.h
> +++ b/gcc/config/arm/aarch-cost-tables.h
> @@ -325,4 +325,105 @@ const struct cpu_cost_table cortexa57_extra_costs =
>     }
>   };
>   
> +const struct cpu_cost_table xgene1_extra_costs =
> +{
> +  /* ALU */
> +  {
> +    0,                 /* arith.  */
> +    0,                 /* logical.  */
> +    0,                 /* shift.  */
> +    COSTS_N_INSNS (1), /* shift_reg.  */
> +    COSTS_N_INSNS (1), /* arith_shift.  */
> +    COSTS_N_INSNS (1), /* arith_shift_reg.  */
> +    COSTS_N_INSNS (1), /* log_shift.  */
> +    COSTS_N_INSNS (1), /* log_shift_reg.  */
> +    COSTS_N_INSNS (1), /* extend.  */
> +    0,                 /* extend_arithm.  */
> +    COSTS_N_INSNS (1), /* bfi.  */
> +    COSTS_N_INSNS (1), /* bfx.  */
> +    0,                 /* clz.  */
> +    COSTS_N_INSNS (1), /* rev.  */
> +    0,                 /* non_exec.  */
> +    true               /* non_exec_costs_exec.  */
> +  },
> +  {
> +    /* MULT SImode */
> +    {
> +      COSTS_N_INSNS (4),       /* simple.  */
> +      COSTS_N_INSNS (4),       /* flag_setting.  */
> +      COSTS_N_INSNS (4),       /* extend.  */
> +      COSTS_N_INSNS (4),       /* add.  */
> +      COSTS_N_INSNS (4),       /* extend_add.  */
> +      COSTS_N_INSNS (20)       /* idiv.  */
> +    },
> +    /* MULT DImode */
> +    {
> +      COSTS_N_INSNS (5),       /* simple.  */
> +      0,                       /* flag_setting (N/A).  */
> +      COSTS_N_INSNS (5),       /* extend.  */
> +      COSTS_N_INSNS (5),       /* add.  */
> +      COSTS_N_INSNS (5),       /* extend_add.  */
> +      COSTS_N_INSNS (21)       /* idiv.  */
> +    }
> +  },
> +  /* LD/ST */
> +  {
> +    COSTS_N_INSNS (5),         /* load.  */
> +    COSTS_N_INSNS (6),         /* load_sign_extend.  */
> +    COSTS_N_INSNS (5),         /* ldrd.  */
> +    COSTS_N_INSNS (5),         /* ldm_1st.  */
> +    1,                         /* ldm_regs_per_insn_1st.  */
> +    1,                         /* ldm_regs_per_insn_subsequent.  */
> +    COSTS_N_INSNS (10),        /* loadf.  */
> +    COSTS_N_INSNS (10),        /* loadd.  */
> +    COSTS_N_INSNS (5),         /* load_unaligned.  */
> +    0,                         /* store.  */
> +    0,                         /* strd.  */
> +    0,                         /* stm_1st.  */
> +    1,                         /* stm_regs_per_insn_1st.  */
> +    1,                         /* stm_regs_per_insn_subsequent.  */
> +    0,                         /* storef.  */
> +    0,                         /* stored.  */
> +    0,                         /* store_unaligned.  */
> +  },
> +  {
> +    /* FP SFmode */
> +    {
> +      COSTS_N_INSNS (23),      /* div.  */
> +      COSTS_N_INSNS (5),       /* mult.  */
> +      COSTS_N_INSNS (5),       /* mult_addsub. */
> +      COSTS_N_INSNS (5),       /* fma.  */
> +      COSTS_N_INSNS (5),       /* addsub.  */
> +      COSTS_N_INSNS (2),       /* fpconst. */
> +      COSTS_N_INSNS (3),       /* neg.  */
> +      COSTS_N_INSNS (2),       /* compare.  */
> +      COSTS_N_INSNS (6),       /* widen.  */
> +      COSTS_N_INSNS (6),       /* narrow.  */
> +      COSTS_N_INSNS (4),       /* toint.  */
> +      COSTS_N_INSNS (4),       /* fromint.  */
> +      COSTS_N_INSNS (4)        /* roundint.  */
> +    },
> +    /* FP DFmode */
> +    {
> +      COSTS_N_INSNS (29),      /* div.  */
> +      COSTS_N_INSNS (5),       /* mult.  */
> +      COSTS_N_INSNS (5),       /* mult_addsub.  */
> +      COSTS_N_INSNS (5),       /* fma.  */
> +      COSTS_N_INSNS (5),       /* addsub.  */
> +      COSTS_N_INSNS (3),       /* fpconst.  */
> +      COSTS_N_INSNS (3),       /* neg.  */
> +      COSTS_N_INSNS (2),       /* compare.  */
> +      COSTS_N_INSNS (6),       /* widen.  */
> +      COSTS_N_INSNS (6),       /* narrow.  */
> +      COSTS_N_INSNS (4),       /* toint.  */
> +      COSTS_N_INSNS (4),       /* fromint.  */
> +      COSTS_N_INSNS (4)        /* roundint.  */
> +    }
> +  },
> +  /* Vector */
> +  {
> +    COSTS_N_INSNS (1)  /* alu.  */
> +  }
> +};
> +
>   #endif /* GCC_AARCH_COST_TABLES_H */