From patchwork Tue Oct 7 05:25:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hurugalawadi, Naveen" X-Patchwork-Id: 397011 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 393351400B7 for ; Tue, 7 Oct 2014 16:26:12 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=WBJbXl6j5uOAsO3KTvuzGL0lEPSPvSoXBnBs9AD6wIXMVXU4vL ANb1TLQ9E0aZ6WM+v/vSyTMLIx0P98AZlzCKxjMYDQLgPbm07rI5y7khOJBCpP+R OZ0MhWJyWBLxkGr7rmMmG4C5AU4B8JgyAKc6kjCTNVajfQg0uQDqnVCMo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; s= default; bh=KNCWYFvN7jM9tI1aKiRZzNf0uuk=; b=grhfiMuGLNU3buePivCC cczIuSpmGvP+9Z42n1Zvri3BL4kGmTET1Yd5O9FB2VykRU/6eRcGuZxPL65WroyN OS2hQ7S+yBHntkaILK5OuaMK25nV4KSKmPL+U8Q5bGeTesNRCaFCJy25BHkXyJ0L pO8J98U+B+CdNW3NVY/hiH8= Received: (qmail 6936 invoked by alias); 7 Oct 2014 05:26:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6924 invoked by uid 89); 7 Oct 2014 05:26:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS autolearn=ham version=3.3.2 X-HELO: na01-bn1-obe.outbound.protection.outlook.com Received: from mail-bn1on0072.outbound.protection.outlook.com (HELO na01-bn1-obe.outbound.protection.outlook.com) (157.56.110.72) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 07 Oct 2014 05:26:01 +0000 Received: from BY2PR07MB549.namprd07.prod.outlook.com (10.141.217.140) by BY2PR07MB122.namprd07.prod.outlook.com (10.242.46.150) with Microsoft SMTP Server (TLS) id 15.0.1044.10; Tue, 7 Oct 2014 05:25:57 +0000 Received: from BY2PR07MB549.namprd07.prod.outlook.com ([10.141.217.140]) by BY2PR07MB549.namprd07.prod.outlook.com ([10.141.217.140]) with mapi id 15.00.1044.008; Tue, 7 Oct 2014 05:25:56 +0000 From: "Hurugalawadi, Naveen" To: "gcc-patches@gcc.gnu.org" CC: "Pinski, Andrew" Subject: [Patch, MIPS] Add Octeon3 support Date: Tue, 7 Oct 2014 05:25:55 +0000 Message-ID: <1412659579490.88923@caviumnetworks.com> x-ms-exchange-transport-fromentityheader: Hosted x-microsoft-antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR07MB122; x-forefront-prvs: 035748864E x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(199003)(164054003)(377424004)(189002)(31966008)(21056001)(99936001)(99286002)(36756003)(97736003)(92566001)(76482002)(2656002)(101416001)(87936001)(99396003)(46102003)(50986999)(117636001)(40100002)(122556002)(120916001)(85852003)(92726001)(105586002)(19580395003)(19580405001)(80022003)(64706001)(20776003)(106356001)(54356999)(106116001)(86362001)(229853001)(107046002)(4396001)(66066001)(2351001)(95666004)(85306004)(110136001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR07MB122; H:BY2PR07MB549.namprd07.prod.outlook.com; FPR:; MLV:sfv; PTR:InfoNoRecords; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-OriginatorOrg: caviumnetworks.com Hi, This patch adds Cavium octeon3 support in mips. Please review the patch and let us know if there should be any modifications. Submitting the patch on behalf of Andrew Pinski. Thanks, 2014-10-07 Andrew Pinski * config/mips/mips-cpus.def (octeon3): New cpu. * config/mips/mips.c (mips_rtx_cost_data): Add octeon3. (mips_print_operand ): Fix a bug as the mode of the comparison no longer matches mode of the operands. (mips_issue_rate): Handle PROCESSOR_OCTEON3. * config/mips/mips.h (TARGET_OCTEON): Add Octeon3. (TARGET_OCTEON2): Likewise. (TUNE_OCTEON): Add Octeon3. * config/mips/mips.md (processor): Add octeon3. * config/mips/octeon.md (octeon_fpu): New automaton and cpu_unit. (octeon_arith): Add octeon3. (octeon_condmove): Remove. (octeon_condmove_o1): New reservation. (octeon_condmove_o2): New reservation. (octeon_condmove_o3_int_on_cc): New reservation. (octeon_load_o2): Add octeon3. (octeon_cop_o2): Likewise. (octeon_store): Likewise. (octeon_brj_o2): Likewise. (octeon_imul3_o2): Likewise. (octeon_imul_o2): Likewise. (octeon_mfhilo_o2): Likewise. (octeon_imadd_o2): Likewise. (octeon_idiv_o2_si): Likewise. (octeon_idiv_o2_di): Likewise. (octeon_fpu): Add to the automaton. (octeon_fpu): New cpu unit. (octeon_condmove_o2): Check for non floating point modes. (octeon_load_o2): Add prefetchx. (octeon_cop_o2): Don't check for octeon3. (octeon3_faddsubcvt): New reservation. (octeon3_fmul): Likewise. (octeon3_fmadd): Likewise. (octeon3_div_sf): Likewise. (octeon3_div_df): Likewise. (octeon3_sqrt_sf): Likewise. (octeon3_sqrt_df): Likewise. (octeon3_rsqrt_sf): Likewise. (octeon3_rsqrt_df): Likewise. (octeon3_fabsnegmov): Likewise. (octeon_fcond): Likewise. (octeon_fcondmov): Likewise. (octeon_fpmtc1): Likewise. (octeon_fpmfc1): Likewise. (octeon_fpload): Likewise. (octeon_fpstore): Likewise. * config/mips/mips-tables.opt: Regenerate. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 73d5d5a..9b7b517 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,53 @@ +2014-10-06 Andrew Pinski + + * config/mips/mips-cpus.def (octeon3): New cpu. + * config/mips/mips.c (mips_rtx_cost_data): Add octeon3. + (mips_print_operand ): Fix a bug as the mode + of the comparison no longer matches mode of the operands. + (mips_issue_rate): Handle PROCESSOR_OCTEON3. + * config/mips/mips.h (TARGET_OCTEON): Add Octeon3. + (TARGET_OCTEON2): Likewise. + (TUNE_OCTEON): Add Octeon3. + * config/mips/mips.md (processor): Add octeon3. + * config/mips/octeon.md (octeon_fpu): New automaton and cpu_unit. + (octeon_arith): Add octeon3. + (octeon_condmove): Remove. + (octeon_condmove_o1): New reservation. + (octeon_condmove_o2): New reservation. + (octeon_condmove_o3_int_on_cc): New reservation. + (octeon_load_o2): Add octeon3. + (octeon_cop_o2): Likewise. + (octeon_store): Likewise. + (octeon_brj_o2): Likewise. + (octeon_imul3_o2): Likewise. + (octeon_imul_o2): Likewise. + (octeon_mfhilo_o2): Likewise. + (octeon_imadd_o2): Likewise. + (octeon_idiv_o2_si): Likewise. + (octeon_idiv_o2_di): Likewise. + (octeon_fpu): Add to the automaton. + (octeon_fpu): New cpu unit. + (octeon_condmove_o2): Check for non floating point modes. + (octeon_load_o2): Add prefetchx. + (octeon_cop_o2): Don't check for octeon3. + (octeon3_faddsubcvt): New reservation. + (octeon3_fmul): Likewise. + (octeon3_fmadd): Likewise. + (octeon3_div_sf): Likewise. + (octeon3_div_df): Likewise. + (octeon3_sqrt_sf): Likewise. + (octeon3_sqrt_df): Likewise. + (octeon3_rsqrt_sf): Likewise. + (octeon3_rsqrt_df): Likewise. + (octeon3_fabsnegmov): Likewise. + (octeon_fcond): Likewise. + (octeon_fcondmov): Likewise. + (octeon_fpmtc1): Likewise. + (octeon_fpmfc1): Likewise. + (octeon_fpload): Likewise. + (octeon_fpstore): Likewise. + * config/mips/mips-tables.opt: Regenerate. + 2014-10-06 Eric Botcazou * calls.c (expand_call): Do not use the target as the return slot if diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index d5528d3..e2985b8 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -162,4 +162,5 @@ MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, 65, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 5791b41..99d2ed8 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -667,5 +667,8 @@ EnumValue Enum(mips_arch_opt_value) String(octeon2) Value(94) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(95) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(95) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(xlp) Value(96) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 723057e..47a1d65 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -959,6 +959,20 @@ static const struct mips_rtx_cost_data 4, /* branch_cost */ 4 /* memory_latency */ }, + /* Octeon III */ + { + COSTS_N_INSNS (6), /* fp_add */ + COSTS_N_INSNS (6), /* fp_mult_sf */ + COSTS_N_INSNS (7), /* fp_mult_df */ + COSTS_N_INSNS (25), /* fp_div_sf */ + COSTS_N_INSNS (48), /* fp_div_df */ + COSTS_N_INSNS (6), /* int_mult_si */ + COSTS_N_INSNS (6), /* int_mult_di */ + COSTS_N_INSNS (18), /* int_div_si */ + COSTS_N_INSNS (35), /* int_div_di */ + 4, /* branch_cost */ + 4 /* memory_latency */ + }, { /* R3900 */ COSTS_N_INSNS (2), /* fp_add */ COSTS_N_INSNS (4), /* fp_mult_sf */ @@ -13174,6 +13188,7 @@ mips_issue_rate (void) case PROCESSOR_R9000: case PROCESSOR_OCTEON: case PROCESSOR_OCTEON2: + case PROCESSOR_OCTEON3: return 2; case PROCESSOR_SB1: diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index c7b998b..726cd48 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -230,8 +230,10 @@ struct mips_cpu_info { #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \ - || mips_arch == PROCESSOR_OCTEON2) -#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2) + || mips_arch == PROCESSOR_OCTEON2 \ + || mips_arch == PROCESSOR_OCTEON3) +#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \ + || mips_arch == PROCESSOR_OCTEON3) #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ || mips_arch == PROCESSOR_SB1A) #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) @@ -261,7 +263,8 @@ struct mips_cpu_info { #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \ - || mips_tune == PROCESSOR_OCTEON2) + || mips_tune == PROCESSOR_OCTEON2 \ + || mips_tune == PROCESSOR_OCTEON3) #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ || mips_tune == PROCESSOR_SB1A) #define TUNE_P5600 (mips_tune == PROCESSOR_P5600) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d47bb78..4b72546 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -41,6 +41,7 @@ m4k octeon octeon2 + octeon3 r3900 r6000 r4000 diff --git a/gcc/config/mips/octeon.md b/gcc/config/mips/octeon.md index 1d6251c..960894f 100644 --- a/gcc/config/mips/octeon.md +++ b/gcc/config/mips/octeon.md @@ -22,41 +22,55 @@ ;; Octeon is a dual-issue processor that can issue all instructions on ;; pipe0 and a subset on pipe1. -(define_automaton "octeon_main, octeon_mult") +(define_automaton "octeon_main, octeon_mult, octeon_fpu") (define_cpu_unit "octeon_pipe0" "octeon_main") (define_cpu_unit "octeon_pipe1" "octeon_main") (define_cpu_unit "octeon_mult" "octeon_mult") +(define_cpu_unit "octeon_fpu" "octeon_fpu") (define_insn_reservation "octeon_arith" 1 - (and (eq_attr "cpu" "octeon,octeon2") + (and (eq_attr "cpu" "octeon,octeon2,octeon3") (eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop")) "octeon_pipe0 | octeon_pipe1") -(define_insn_reservation "octeon_condmove" 2 - (and (eq_attr "cpu" "octeon,octeon2") +(define_insn_reservation "octeon_condmove_o1" 2 + (and (eq_attr "cpu" "octeon") (eq_attr "type" "condmove")) "octeon_pipe0 | octeon_pipe1") +(define_insn_reservation "octeon_condmove_o2" 3 + (and (eq_attr "cpu" "octeon2,octeon3") + (eq_attr "type" "condmove") + (not (eq_attr "mode" "SF, DF"))) + "octeon_pipe0 | octeon_pipe1") + +;; movt/movf can only issue in pipe1 +(define_insn_reservation "octeon_condmove_o3_int_on_cc" 3 + (and (eq_attr "cpu" "octeon2,octeon3") + (eq_attr "type" "condmove") + (not (eq_attr "mode" "SF, DF"))) + "octeon_pipe1") + (define_insn_reservation "octeon_load_o1" 2 (and (eq_attr "cpu" "octeon") (eq_attr "type" "load,prefetch,mtc,mfc")) "octeon_pipe0") (define_insn_reservation "octeon_load_o2" 3 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "load,prefetch")) "octeon_pipe0") ;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency. ;; Front-end-related ones are 1-cycle on pipe1. Assume front-end for now. (define_insn_reservation "octeon_cop_o2" 1 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "mtc,mfc")) "octeon_pipe1") (define_insn_reservation "octeon_store" 1 - (and (eq_attr "cpu" "octeon,octeon2") + (and (eq_attr "cpu" "octeon,octeon2,octeon3") (eq_attr "type" "store")) "octeon_pipe0") @@ -66,7 +80,7 @@ "octeon_pipe0") (define_insn_reservation "octeon_brj_o2" 2 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "branch,jump,call,trap")) "octeon_pipe1") @@ -76,7 +90,7 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult") (define_insn_reservation "octeon_imul3_o2" 6 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "imul3,pop,clz")) "octeon_pipe1 + octeon_mult") @@ -86,7 +100,7 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult") (define_insn_reservation "octeon_imul_o2" 1 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "imul,mthi,mtlo")) "octeon_pipe1 + octeon_mult") @@ -96,7 +110,7 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult") (define_insn_reservation "octeon_mfhilo_o2" 6 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "mfhi,mflo")) "octeon_pipe1 + octeon_mult") @@ -106,7 +120,7 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3") (define_insn_reservation "octeon_imadd_o2" 1 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "type" "imadd")) "octeon_pipe1 + octeon_mult") @@ -116,13 +130,13 @@ "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71") (define_insn_reservation "octeon_idiv_o2_si" 18 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "mode" "SI") (eq_attr "type" "idiv")) "octeon_pipe1 + octeon_mult, octeon_mult*17") (define_insn_reservation "octeon_idiv_o2_di" 35 - (and (eq_attr "cpu" "octeon2") + (and (eq_attr "cpu" "octeon2,octeon3") (eq_attr "mode" "DI") (eq_attr "type" "idiv")) "octeon_pipe1 + octeon_mult, octeon_mult*34") @@ -131,6 +145,95 @@ ;; patterns. (define_insn_reservation "octeon_unknown" 1 - (and (eq_attr "cpu" "octeon,octeon2") + (and (eq_attr "cpu" "octeon,octeon2,octeon3") (eq_attr "type" "unknown,multi,atomic,syncloop")) "octeon_pipe0 + octeon_pipe1") + +;; Octeon3 FPU + +(define_insn_reservation "octeon3_faddsubcvt" 4 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fadd, fcvt")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon3_fmul" 5 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fmul")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon3_fmadd" 9 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fmadd")) + "octeon_pipe1 + octeon_fpu, octeon_fpu") + +(define_insn_reservation "octeon3_div_sf" 12 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fdiv, frdiv") + (eq_attr "mode" "SF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*8") + +(define_insn_reservation "octeon3_div_df" 22 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fdiv, frdiv") + (eq_attr "mode" "SF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*18") + +(define_insn_reservation "octeon3_sqrt_sf" 16 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fsqrt") + (eq_attr "mode" "SF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*12") + +(define_insn_reservation "octeon3_sqrt_df" 30 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fsqrt") + (eq_attr "mode" "DF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*26") + +(define_insn_reservation "octeon3_rsqrt_sf" 27 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "frsqrt") + (eq_attr "mode" "SF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*23") + +(define_insn_reservation "octeon3_rsqrt_df" 51 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "frsqrt") + (eq_attr "mode" "DF")) + "octeon_pipe1 + octeon_fpu, octeon_fpu*47") + +(define_insn_reservation "octeon3_fabsnegmov" 2 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fabs, fneg, fmove")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fcond" 1 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fcmp")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fcondmov" 2 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "condmove") + (eq_attr "mode" "SF,DF")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fpmtc1" 2 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "mtc")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fpmfc1" 6 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "mtc")) + "octeon_pipe1 + octeon_fpu") + +(define_insn_reservation "octeon_fpload" 3 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fpload,fpidxload")) + "octeon_pipe0 + octeon_fpu") + +(define_insn_reservation "octeon_fpstore" 3 + (and (eq_attr "cpu" "octeon3") + (eq_attr "type" "fpstore,fpidxstore")) + "octeon_pipe0 + octeon_pipe1")