From patchwork Fri Aug 29 18:28:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 384351 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 07E4B14013B for ; Sat, 30 Aug 2014 04:28:45 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type:mime-version :content-transfer-encoding; q=dns; s=default; b=LQhLq57bvxKhemof zifuEsk7KO4UmJPYqxktCzgLT8j0Ip1PsCal7i7gEc9wlqN5/OAfT1a9zNdjW3CV s6g9lqlHlD967vJGVKgdDBGdEsi5Ip3dgIuiw2b4dJ5aGMhs6MhT/lskKfleXwx2 DonsK/6tAz1+JeLaeU2HIL92SZw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type:mime-version :content-transfer-encoding; s=default; bh=lmvmA1aE5CnCg3pODG6h7M tMEWY=; b=IVQX/VXRzG702NGsuFjo7KjuYtgOwOnhQpv5ILySd5XwOfO/ae4w84 VYuHjeQQMrpb4fLGeEjM20G/kDc/D0LnEBYV5/Fn9cDeh9uTM61Sq3xMSXXggiXo oP1Az1QHFXgTCay/zDMC5wy1zl88+Pe/PbnTF8BA2IZ53B5FeCWD0= Received: (qmail 17961 invoked by alias); 29 Aug 2014 18:28:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17941 invoked by uid 89); 29 Aug 2014 18:28:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e7.ny.us.ibm.com Received: from e7.ny.us.ibm.com (HELO e7.ny.us.ibm.com) (32.97.182.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Fri, 29 Aug 2014 18:28:32 +0000 Received: from /spool/local by e7.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 29 Aug 2014 14:28:28 -0400 Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id BA20C38C805C for ; Fri, 29 Aug 2014 14:28:27 -0400 (EDT) Received: from d01av04.pok.ibm.com (d01av04.pok.ibm.com [9.56.224.64]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id s7TISRja50331688 for ; Fri, 29 Aug 2014 18:28:27 GMT Received: from d01av04.pok.ibm.com (localhost [127.0.0.1]) by d01av04.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s7TISRGm006666 for ; Fri, 29 Aug 2014 14:28:27 -0400 Received: from [9.50.19.136] ([9.50.19.136]) by d01av04.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s7TISQKL006579; Fri, 29 Aug 2014 14:28:26 -0400 Message-ID: <1409336926.25590.84.camel@gnopaine> Subject: [PATCH, rs6000] A few more vector builtins From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com Date: Fri, 29 Aug 2014 13:28:46 -0500 Mime-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14082918-5806-0000-0000-0000005647D6 X-IsSubscribed: yes Hi, This is the last in the current series of new vector built-ins. This group adds vec_ctf, vec_cts, and vec_ctu for vector double and vector long long. Additionally, it adds documentation for the built-ins added in my last patch, since I forgot to add it then... /oops Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions. Ok for trunk? Thanks, Bill [gcc] 2014-08-29 Bill Schmidt * config/rs6000/rs6000-builtin.def (XVCVSXDDP_SCALE): New built-in definition. (XVCVUXDDP_SCALE): Likewise. (XVCVDPSXDS_SCALE): Likewise. (XVCVDPUXDS_SCALE): Likewise. * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add entries for VSX_BUILTIN_XVCVSXDDP_SCALE, VSX_BUILTIN_XVCVUXDDP_SCALE, VSX_BUILTIN_XVCVDPSXDS_SCALE, and VSX_BUILTIN_XVCVDPUXDS_SCALE. * config/rs6000/rs6000-protos.h (rs6000_scale_v2df): New prototype. * config/rs6000/rs6000.c (real.h): New include. (rs6000_scale_v2df): New function. * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSXDDP): New unspec. (UNSPEC_VSX_XVCVUXDDP): Likewise. (UNSPEC_VSX_XVCVDPSXDS): Likewise. (UNSPEC_VSX_XVCVDPUXDS): Likewise. (vsx_xvcvsxddp_scale): New define_expand. (vsx_xvcvsxddp): New define_insn. (vsx_xvcvuxddp_scale): New define_expand. (vsx_xvcvuxddp): New define_insn. (vsx_xvcvdpsxds_scale): New define_expand. (vsx_xvcvdpsxds): New define_insn. (vsx_xvcvdpuxds_scale): New define_expand. (vsx_xvcvdpuxds): New define_insn. * doc/extend.texi (vec_ctf): Add new prototypes. (vec_cts): Likewise. (vec_ctu): Likewise. (vec_splat): Likewise. (vec_div): Likewise. (vec_mul): Likewise. [gcc/testsuite] 2014-08-29 Bill Schmidt * gcc.target/powerpc/builtins-1.c: Add tests for vec_ctf, vec_cts, and vec_ctu. * gcc.target/powerpc/builtins-2.c: Likewise. Index: gcc/config/rs6000/rs6000-builtin.def =================================================================== --- gcc/config/rs6000/rs6000-builtin.def (revision 214735) +++ gcc/config/rs6000/rs6000-builtin.def (working copy) @@ -1264,6 +1264,11 @@ BU_VSX_2 (DIV_V2DI, "div_2di", CO BU_VSX_2 (UDIV_V2DI, "udiv_2di", CONST, vsx_udiv_v2di) BU_VSX_2 (MUL_V2DI, "mul_2di", CONST, vsx_mul_v2di) +BU_VSX_2 (XVCVSXDDP_SCALE, "xvcvsxddp_scale", CONST, vsx_xvcvsxddp_scale) +BU_VSX_2 (XVCVUXDDP_SCALE, "xvcvuxddp_scale", CONST, vsx_xvcvuxddp_scale) +BU_VSX_2 (XVCVDPSXDS_SCALE, "xvcvdpsxds_scale", CONST, vsx_xvcvdpsxds_scale) +BU_VSX_2 (XVCVDPUXDS_SCALE, "xvcvdpuxds_scale", CONST, vsx_xvcvdpuxds_scale) + /* VSX abs builtin functions. */ BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2) BU_VSX_A (XVNABSDP, "xvnabsdp", CONST, vsx_nabsv2df2) Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 214735) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -1151,6 +1151,10 @@ const struct altivec_builtin_types altivec_overloa RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, + RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, + { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, + RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, @@ -1157,8 +1161,12 @@ const struct altivec_builtin_types altivec_overloa RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, + RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h (revision 214735) +++ gcc/config/rs6000/rs6000-protos.h (working copy) @@ -65,6 +65,7 @@ extern void altivec_expand_stvx_be (rtx, rtx, enum extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned); extern void rs6000_expand_extract_even (rtx, rtx, rtx); extern void rs6000_expand_interleave (rtx, rtx, rtx, bool); +extern void rs6000_scale_v2df (rtx, rtx, int); extern void build_mask64_2_operands (rtx, rtx *); extern int expand_block_clear (rtx[]); extern int expand_block_move (rtx[]); Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 214735) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -81,6 +81,7 @@ #include "builtins.h" #include "context.h" #include "tree-pass.h" +#include "real.h" #if TARGET_XCOFF #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ #endif @@ -31245,6 +31246,23 @@ rs6000_expand_interleave (rtx target, rtx op0, rtx rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm); } +/* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */ +void +rs6000_scale_v2df (rtx tgt, rtx src, int scale) +{ + HOST_WIDE_INT hwi_scale (scale); + REAL_VALUE_TYPE r_pow; + rtvec v = rtvec_alloc (2); + rtx elt; + rtx scale_vec = gen_reg_rtx (V2DFmode); + (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale); + elt = CONST_DOUBLE_FROM_REAL_VALUE (r_pow, DFmode); + RTVEC_ELT (v, 0) = elt; + RTVEC_ELT (v, 1) = elt; + rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v)); + emit_insn (gen_mulv2df3 (tgt, src, scale_vec)); +} + /* Return an RTX representing where to find the function value of a function returning MODE. */ static rtx Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 214735) +++ gcc/config/rs6000/vsx.md (working copy) @@ -264,6 +264,10 @@ UNSPEC_VSX_DIVSD UNSPEC_VSX_DIVUD UNSPEC_VSX_MULSD + UNSPEC_VSX_XVCVSXDDP + UNSPEC_VSX_XVCVUXDDP + UNSPEC_VSX_XVCVDPSXDS + UNSPEC_VSX_XVCVDPUXDS ]) ;; VSX moves @@ -1356,6 +1360,102 @@ "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) +;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long) + +(define_expand "vsx_xvcvsxddp_scale" + [(match_operand:V2DF 0 "vsx_register_operand" "") + (match_operand:V2DI 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + int scale = INTVAL(operands[2]); + emit_insn (gen_vsx_xvcvsxddp (op0, op1)); + if (scale != 0) + rs6000_scale_v2df (op0, op0, -scale); + DONE; +}) + +(define_insn "vsx_xvcvsxddp" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVSXDDP))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvsxddp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvuxddp_scale" + [(match_operand:V2DF 0 "vsx_register_operand" "") + (match_operand:V2DI 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + int scale = INTVAL(operands[2]); + emit_insn (gen_vsx_xvcvuxddp (op0, op1)); + if (scale != 0) + rs6000_scale_v2df (op0, op0, -scale); + DONE; +}) + +(define_insn "vsx_xvcvuxddp" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVUXDDP))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvuxddp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvdpsxds_scale" + [(match_operand:V2DI 0 "vsx_register_operand" "") + (match_operand:V2DF 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = gen_reg_rtx (V2DFmode); + int scale = INTVAL(operands[2]); + if (scale != 0) + rs6000_scale_v2df (tmp, op1, scale); + emit_insn (gen_vsx_xvcvdpsxds (op0, tmp)); + DONE; +}) + +(define_insn "vsx_xvcvdpsxds" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVDPSXDS))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvdpsxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvdpuxds_scale" + [(match_operand:V2DI 0 "vsx_register_operand" "") + (match_operand:V2DF 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = gen_reg_rtx (V2DFmode); + int scale = INTVAL(operands[2]); + if (scale != 0) + rs6000_scale_v2df (tmp, op1, scale); + emit_insn (gen_vsx_xvcvdpuxds (op0, tmp)); + DONE; +}) + +(define_insn "vsx_xvcvdpuxds" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVDPUXDS))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvdpuxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + ;; Convert from 64-bit to 32-bit types ;; Note, favor the Altivec registers since the usual use of these instructions ;; is in vector converts and we need to use the Altivec vperm instruction. Index: gcc/doc/extend.texi =================================================================== --- gcc/doc/extend.texi (revision 214735) +++ gcc/doc/extend.texi (working copy) @@ -13882,6 +13882,8 @@ vector float vec_cpsgn (vector float, vector float vector float vec_ctf (vector unsigned int, const int); vector float vec_ctf (vector signed int, const int); +vector double vec_ctf (vector unsigned long, const int); +vector double vec_ctf (vector signed long, const int); vector float vec_vcfsx (vector signed int, const int); @@ -13888,8 +13890,10 @@ vector float vec_vcfsx (vector signed int, const i vector float vec_vcfux (vector unsigned int, const int); vector signed int vec_cts (vector float, const int); +vector signed long vec_cts (vector double, const int); vector unsigned int vec_ctu (vector float, const int); +vector unsigned long vec_ctu (vector double, const int); void vec_dss (const int); @@ -14725,6 +14729,8 @@ vector float vec_splat (vector float, const int); vector signed int vec_splat (vector signed int, const int); vector unsigned int vec_splat (vector unsigned int, const int); vector bool int vec_splat (vector bool int, const int); +vector signed long vec_splat (vector signed long, const int); +vector unsigned long vec_splat (vector unsigned long, const int); vector signed char vec_splats (signed char); vector unsigned char vec_splats (unsigned char); @@ -15461,6 +15467,8 @@ vector bool long vec_cmplt (vector double, vector vector double vec_cpsgn (vector double, vector double); vector float vec_div (vector float, vector float); vector double vec_div (vector double, vector double); +vector long vec_div (vector long, vector long); +vector unsigned long vec_div (vector unsigned long, vector unsigned long); vector double vec_floor (vector double); vector double vec_ld (int, const vector double *); vector double vec_ld (int, const double *); @@ -15487,6 +15495,8 @@ vector float vec_msub (vector float, vector float, vector double vec_msub (vector double, vector double, vector double); vector float vec_mul (vector float, vector float); vector double vec_mul (vector double, vector double); +vector long vec_mul (vector long, vector long); +vector unsigned long vec_mul (vector unsigned long, vector unsigned long); vector float vec_nearbyint (vector float); vector double vec_nearbyint (vector double); vector float vec_nmadd (vector float, vector float, vector float); Index: gcc/testsuite/gcc.target/powerpc/builtins-1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/builtins-1.c (revision 214735) +++ gcc/testsuite/gcc.target/powerpc/builtins-1.c (working copy) @@ -157,5 +157,10 @@ int main () vector long long l8 = vec_mul (l3, l4); vector unsigned long long u6 = vec_mul (u3, u4); + vector double dh = vec_ctf (la, -2); + vector double di = vec_ctf (ua, 2); + vector long long l9 = vec_cts (dh, -2); + vector unsigned long long u7 = vec_ctu (di, 2); + return 0; } Index: gcc/testsuite/gcc.target/powerpc/builtins-2.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/builtins-2.c (revision 214735) +++ gcc/testsuite/gcc.target/powerpc/builtins-2.c (working copy) @@ -34,5 +34,14 @@ int main () || ue[0] != 27L || ue[1] != 27L || uf[0] != 14L || uf[1] != 14L) abort (); + vector double da = vec_ctf (sa, -2); + vector double db = vec_ctf (ua, 2); + vector long long sg = vec_cts (da, -2); + vector unsigned long long ug = vec_ctu (db, 2); + + if (da[0] != 108.0 || da[1] != -56.0 || db[0] != 6.75 || db[1] != 3.5 + || sg[0] != 27L || sg[1] != -14L || ug[0] != 27L || ug[1] != 14L) + abort (); + return 0; }