From patchwork Thu Apr 3 17:58:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 336698 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E1DD714008C for ; Fri, 4 Apr 2014 04:58:49 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=fFd e6aZORIHcxVjYfZmWl0E5e2M3kLrV6M7EHcG1JSLKgT9gBok+ZZjq7X3thKv3ATD 6pug2lye4N2kOO0QiQN+uDsHltmKpscOHjFicpy0yy6TXKmQapF3B2ufnw7ibs3D VwrV+DZBWvo9+MjDO64+gcuIueZ0gzs1fK4CGCTA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; s=default; bh=NYg8UX0Nb e7uELU0GlfECZchdmk=; b=BEn9/vMQnw34ye5PzN5ydTb7/SrZ5BQ9O7S/qa8MO GoYb2QI34pqY9jQLFNzY/6isphDIbinMb4YbRotT1daTcn8IN/Y0LI6eWTeq4sz2 gjeOzGUw3TjPCCV6u9pn6emEs2KqQt7XNlGnNHASxKyvi8fW77UuLElbRiQfaXK9 ZA= Received: (qmail 1100 invoked by alias); 3 Apr 2014 17:58:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 1085 invoked by uid 89); 3 Apr 2014 17:58:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e8.ny.us.ibm.com Received: from e8.ny.us.ibm.com (HELO e8.ny.us.ibm.com) (32.97.182.138) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 03 Apr 2014 17:58:42 +0000 Received: from /spool/local by e8.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 3 Apr 2014 13:58:39 -0400 Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id B21A038C8045 for ; Thu, 3 Apr 2014 13:58:38 -0400 (EDT) Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by b01cxnp22036.gho.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s33HwcRh62193850 for ; Thu, 3 Apr 2014 17:58:38 GMT Received: from d01av03.pok.ibm.com (localhost [127.0.0.1]) by d01av03.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s33HwcVP009433 for ; Thu, 3 Apr 2014 13:58:38 -0400 Received: from [9.50.20.76] (dyn9050020076.mts.ibm.com [9.50.20.76] (may be forged)) by d01av03.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s33Hwcnl009390; Thu, 3 Apr 2014 13:58:38 -0400 Message-ID: <1396547919.5401.3.camel@gnopaine> Subject: [4.8, PATCH 28/26] Backport Power8 and LE support: Fix for SPE (PR60735) From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com Date: Thu, 03 Apr 2014 12:58:39 -0500 Mime-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14040317-0320-0000-0000-000002D87BDD X-IsSubscribed: yes Hi, This patch (diff-pr60735) adds to the 4.8 PowerPC backport patch series with a backported fix for PR60735, an unrecognized insn problem for SPE. Thanks, Bill [gcc] 2014-04-03 Bill Schmidt Back port mainline subversion id 209025. 2014-04-02 Michael Meissner PR target/60735 * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have software floating point or no floating point registers, do not allow any type in the FPRs. Eliminate a test for SPE SIMD types in GPRs that occurs after we tested for GPRs that would never be true. * config/rs6000/rs6000.md (mov_softfloat32, FMOVE64): Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, specifically allow DDmode, since that does not use the SPE SIMD instructions. Index: gcc-4_8-test2/gcc/config/rs6000/rs6000.c =================================================================== --- gcc-4_8-test2.orig/gcc/config/rs6000/rs6000.c +++ gcc-4_8-test2/gcc/config/rs6000/rs6000.c @@ -1733,6 +1733,9 @@ rs6000_hard_regno_mode_ok (int regno, en modes and DImode. */ if (FP_REGNO_P (regno)) { + if (TARGET_SOFT_FLOAT || !TARGET_FPRS) + return 0; + if (SCALAR_FLOAT_MODE_P (mode) && (mode != TDmode || (regno % 2) == 0) && FP_REGNO_P (last_regno)) @@ -1761,10 +1764,6 @@ rs6000_hard_regno_mode_ok (int regno, en return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) || mode == V1TImode); - /* ...but GPRs can hold SIMD data on the SPE in one register. */ - if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) - return 1; - /* We cannot put non-VSX TImode or PTImode anywhere except general register and it must be able to fit within the register set. */ Index: gcc-4_8-test2/gcc/config/rs6000/rs6000.md =================================================================== --- gcc-4_8-test2.orig/gcc/config/rs6000/rs6000.md +++ gcc-4_8-test2/gcc/config/rs6000/rs6000.md @@ -9428,8 +9428,9 @@ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r") (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] "! TARGET_POWERPC64 - && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) - || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) + && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) + || TARGET_SOFT_FLOAT + || (mode == DDmode && TARGET_E500_DOUBLE)) && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" "#"