@@ -18,226 +18,6 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-
-; Main data types used by the insntructions
-
-(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI"
- (const_string "unknown"))
-
-
-; Classification of AdvSIMD instructions for scheduling purposes.
-; Do not set this attribute and the "v8type" attribute together in
-; any instruction pattern.
-
-; simd_abd integer absolute difference and accumulate.
-; simd_abdl integer absolute difference and accumulate (long).
-; simd_adal integer add and accumulate (long).
-; simd_add integer addition/subtraction.
-; simd_addl integer addition/subtraction (long).
-; simd_addlv across lanes integer sum (long).
-; simd_addn integer addition/subtraction (narrow).
-; simd_addn2 integer addition/subtraction (narrow, high).
-; simd_addv across lanes integer sum.
-; simd_cls count leading sign/zero bits.
-; simd_cmp compare / create mask.
-; simd_cnt population count.
-; simd_dup duplicate element.
-; simd_dupgp duplicate general purpose register.
-; simd_ext bitwise extract from pair.
-; simd_fabd floating point absolute difference.
-; simd_fadd floating point add/sub.
-; simd_fcmp floating point compare.
-; simd_fcvti floating point convert to integer.
-; simd_fcvtl floating-point convert upsize.
-; simd_fcvtn floating-point convert downsize (narrow).
-; simd_fcvtn2 floating-point convert downsize (narrow, high).
-; simd_fdiv floating point division.
-; simd_fminmax floating point min/max.
-; simd_fminmaxv across lanes floating point min/max.
-; simd_fmla floating point multiply-add.
-; simd_fmla_elt floating point multiply-add (by element).
-; simd_fmul floating point multiply.
-; simd_fmul_elt floating point multiply (by element).
-; simd_fnegabs floating point neg/abs.
-; simd_frecpe floating point reciprocal estimate.
-; simd_frecps floating point reciprocal step.
-; simd_frecpx floating point reciprocal exponent.
-; simd_frint floating point round to integer.
-; simd_fsqrt floating point square root.
-; simd_icvtf integer convert to floating point.
-; simd_ins insert element.
-; simd_insgp insert general purpose register.
-; simd_load1 load multiple structures to one register (LD1).
-; simd_load1r load single structure to all lanes of one register (LD1R).
-; simd_load1s load single structure to one lane of one register (LD1 [index]).
-; simd_load2 load multiple structures to two registers (LD1, LD2).
-; simd_load2r load single structure to all lanes of two registers (LD1R, LD2R).
-; simd_load2s load single structure to one lane of two registers (LD2 [index]).
-; simd_load3 load multiple structures to three registers (LD1, LD3).
-; simd_load3r load single structure to all lanes of three registers (LD3R).
-; simd_load3s load single structure to one lane of three registers (LD3 [index]).
-; simd_load4 load multiple structures to four registers (LD1, LD2, LD4).
-; simd_load4r load single structure to all lanes of four registers (LD4R).
-; simd_load4s load single structure to one lane of four registers (LD4 [index]).
-; simd_logic logical operation.
-; simd_logic_imm logcial operation (immediate).
-; simd_minmax integer min/max.
-; simd_minmaxv across lanes integer min/max,
-; simd_mla integer multiply-accumulate.
-; simd_mla_elt integer multiply-accumulate (by element).
-; simd_mlal integer multiply-accumulate (long).
-; simd_mlal_elt integer multiply-accumulate (by element, long).
-; simd_move move register.
-; simd_move_imm move immediate.
-; simd_movgp move element to general purpose register.
-; simd_mul integer multiply.
-; simd_mul_elt integer multiply (by element).
-; simd_mull integer multiply (long).
-; simd_mull_elt integer multiply (by element, long).
-; simd_negabs integer negate/absolute.
-; simd_rbit bitwise reverse.
-; simd_rcpe integer reciprocal estimate.
-; simd_rcps integer reciprocal square root.
-; simd_rev element reverse.
-; simd_sat_add integer saturating addition/subtraction.
-; simd_sat_mlal integer saturating multiply-accumulate (long).
-; simd_sat_mlal_elt integer saturating multiply-accumulate (by element, long).
-; simd_sat_mul integer saturating multiply.
-; simd_sat_mul_elt integer saturating multiply (by element).
-; simd_sat_mull integer saturating multiply (long).
-; simd_sat_mull_elt integer saturating multiply (by element, long).
-; simd_sat_negabs integer saturating negate/absolute.
-; simd_sat_shift integer saturating shift.
-; simd_sat_shift_imm integer saturating shift (immediate).
-; simd_sat_shiftn_imm integer saturating shift (narrow, immediate).
-; simd_sat_shiftn2_imm integer saturating shift (narrow, high, immediate).
-; simd_shift shift register/vector.
-; simd_shift_acc shift accumulate.
-; simd_shift_imm shift immediate.
-; simd_shift_imm_acc shift immediate and accumualte.
-; simd_shiftl shift register/vector (long).
-; simd_shiftl_imm shift register/vector (long, immediate).
-; simd_shiftn_imm shift register/vector (narrow, immediate).
-; simd_shiftn2_imm shift register/vector (narrow, high, immediate).
-; simd_store1 store multiple structures from one register (ST1).
-; simd_store1s store single structure from one lane of one register (ST1 [index]).
-; simd_store2 store multiple structures from two registers (ST1, ST2).
-; simd_store2s store single structure from one lane of two registers (ST2 [index]).
-; simd_store3 store multiple structures from three registers (ST1, ST3).
-; simd_store3s store single structure from one lane of three register (ST3 [index]).
-; simd_store4 store multiple structures from four registers (ST1, ST2, ST4).
-; simd_store4s store single structure from one lane for four registers (ST4 [index]).
-; simd_tbl table lookup.
-; simd_trn transpose.
-; simd_uzp unzip.
-; simd_zip zip.
-
-(define_attr "simd_type"
- "simd_abd,\
- simd_abdl,\
- simd_adal,\
- simd_add,\
- simd_addl,\
- simd_addlv,\
- simd_addn,\
- simd_addn2,\
- simd_addv,\
- simd_cls,\
- simd_cmp,\
- simd_cnt,\
- simd_dup,\
- simd_dupgp,\
- simd_ext,\
- simd_fabd,\
- simd_fadd,\
- simd_fcmp,\
- simd_fcvti,\
- simd_fcvtl,\
- simd_fcvtn,\
- simd_fcvtn2,\
- simd_fdiv,\
- simd_fminmax,\
- simd_fminmaxv,\
- simd_fmla,\
- simd_fmla_elt,\
- simd_fmul,\
- simd_fmul_elt,\
- simd_fnegabs,\
- simd_frecpe,\
- simd_frecps,\
- simd_frecpx,\
- simd_frint,\
- simd_fsqrt,\
- simd_icvtf,\
- simd_ins,\
- simd_insgp,\
- simd_load1,\
- simd_load1r,\
- simd_load1s,\
- simd_load2,\
- simd_load2r,\
- simd_load2s,\
- simd_load3,\
- simd_load3r,\
- simd_load3s,\
- simd_load4,\
- simd_load4r,\
- simd_load4s,\
- simd_logic,\
- simd_logic_imm,\
- simd_minmax,\
- simd_minmaxv,\
- simd_mla,\
- simd_mla_elt,\
- simd_mlal,\
- simd_mlal_elt,\
- simd_movgp,\
- simd_move,\
- simd_move_imm,\
- simd_mul,\
- simd_mul_elt,\
- simd_mull,\
- simd_mull_elt,\
- simd_negabs,\
- simd_rbit,\
- simd_rcpe,\
- simd_rcps,\
- simd_rev,\
- simd_sat_add,\
- simd_sat_mlal,\
- simd_sat_mlal_elt,\
- simd_sat_mul,\
- simd_sat_mul_elt,\
- simd_sat_mull,\
- simd_sat_mull_elt,\
- simd_sat_negabs,\
- simd_sat_shift,\
- simd_sat_shift_imm,\
- simd_sat_shiftn_imm,\
- simd_sat_shiftn2_imm,\
- simd_shift,\
- simd_shift_acc,\
- simd_shift_imm,\
- simd_shift_imm_acc,\
- simd_shiftl,\
- simd_shiftl_imm,\
- simd_shiftn_imm,\
- simd_shiftn2_imm,\
- simd_store1,\
- simd_store1s,\
- simd_store2,\
- simd_store2s,\
- simd_store3,\
- simd_store3s,\
- simd_store4,\
- simd_store4s,\
- simd_tbl,\
- simd_trn,\
- simd_uzp,\
- simd_zip,\
- none"
- (const_string "none"))
-
(define_expand "mov<mode>"
[(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "")
(match_operand:VALL 1 "aarch64_simd_general_operand" ""))]
@@ -268,9 +48,7 @@ (define_insn "aarch64_simd_dup<mode>"
"@
dup\\t%0.<Vtype>, %<vw>1
dup\\t%0.<Vtype>, %1.<Vetype>[0]"
- [(set_attr "simd_type" "simd_dupgp, simd_dup")
- (set_attr "type" "neon_from_gp<q>, neon_dup<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_from_gp<q>, neon_dup<q>")]
)
(define_insn "aarch64_simd_dup<mode>"
@@ -278,9 +56,7 @@ (define_insn "aarch64_simd_dup<mode>"
(vec_duplicate:VDQF (match_operand:<VEL> 1 "register_operand" "w")))]
"TARGET_SIMD"
"dup\\t%0.<Vtype>, %1.<Vetype>[0]"
- [(set_attr "simd_type" "simd_dup")
- (set_attr "type" "neon_dup<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_dup<q>")]
)
(define_insn "aarch64_dup_lane<mode>"
@@ -292,9 +68,7 @@ (define_insn "aarch64_dup_lane<mode>"
)))]
"TARGET_SIMD"
"dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
- [(set_attr "simd_type" "simd_dup")
- (set_attr "type" "neon_dup<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_dup<q>")]
)
(define_insn "aarch64_dup_lane_<vswap_width_name><mode>"
@@ -306,9 +80,7 @@ (define_insn "aarch64_dup_lane_<vswap_wi
)))]
"TARGET_SIMD"
"dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
- [(set_attr "simd_type" "simd_dup")
- (set_attr "type" "neon_dup<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_dup<q>")]
)
(define_insn "*aarch64_simd_mov<mode>"
@@ -334,11 +106,9 @@ (define_insn "*aarch64_simd_mov<mode>"
default: gcc_unreachable ();
}
}
- [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm")
- (set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\
+ [(set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\
neon_logic<q>, neon_to_gp<q>, neon_from_gp<q>,\
- mov_reg, neon_move<q>")
- (set_attr "simd_mode" "<MODE>")]
+ mov_reg, neon_move<q>")]
)
(define_insn "*aarch64_simd_mov<mode>"
@@ -368,11 +138,9 @@ (define_insn "*aarch64_simd_mov<mode>"
gcc_unreachable ();
}
}
- [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm")
- (set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\
+ [(set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\
neon_logic<q>, multiple, multiple, multiple,\
neon_move<q>")
- (set_attr "simd_mode" "<MODE>")
(set_attr "length" "4,4,4,8,8,8,4")]
)
@@ -451,9 +219,7 @@ (define_insn "aarch64_simd_mov_from_<mod
(match_operand:VQ 2 "vect_par_cnst_lo_half" "")))]
"TARGET_SIMD && reload_completed"
"umov\t%0, %1.d[0]"
- [(set_attr "simd_type" "simd_movgp")
- (set_attr "type" "neon_to_gp<q>")
- (set_attr "simd_mode" "<MODE>")
+ [(set_attr "type" "neon_to_gp<q>")
(set_attr "length" "4")
])
@@ -464,9 +230,7 @@ (define_insn "aarch64_simd_mov_from_<mod
(match_operand:VQ 2 "vect_par_cnst_hi_half" "")))]
"TARGET_SIMD && reload_completed"
"umov\t%0, %1.d[1]"
- [(set_attr "simd_type" "simd_movgp")
- (set_attr "type" "neon_to_gp<q>")
- (set_attr "simd_mode" "<MODE>")
+ [(set_attr "type" "neon_to_gp<q>")
(set_attr "length" "4")
])
@@ -476,9 +240,7 @@ (define_insn "orn<mode>3"
(match_operand:VDQ 2 "register_operand" "w")))]
"TARGET_SIMD"
"orn\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
- [(set_attr "simd_type" "simd_logic")
- (set_attr "type" "neon_logic<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_logic<q>")]
)
(define_insn "bic<mode>3"
@@ -487,9 +249,7 @@ (define_insn "bic<mode>3"
(match_operand:VDQ 2 "register_operand" "w")))]
"TARGET_SIMD"
"bic\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
- [(set_attr "simd_type" "simd_logic")
- (set_attr "type" "neon_logic<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_logic<q>")]
)
(define_insn "add<mode>3"
@@ -498,9 +258,7 @@ (define_insn "add<mode>3"
(match_operand:VDQ 2 "register_operand" "w")))]
"TARGET_SIMD"
"add\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_add")
- (set_attr "type" "neon_add<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_add<q>")]
)
(define_insn "sub<mode>3"
@@ -509,9 +267,7 @@ (define_insn "sub<mode>3"
(match_operand:VDQ 2 "register_operand" "w")))]
"TARGET_SIMD"
"sub\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_add")
- (set_attr "type" "neon_sub<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sub<q>")]
)
(define_insn "mul<mode>3"
@@ -520,9 +276,7 @@ (define_insn "mul<mode>3"
(match_operand:VDQM 2 "register_operand" "w")))]
"TARGET_SIMD"
"mul\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_mul")
- (set_attr "type" "neon_mul_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mul_<Vetype><q>")]
)
(define_insn "*aarch64_mul3_elt<mode>"
@@ -535,9 +289,7 @@ (define_insn "*aarch64_mul3_elt<mode>"
(match_operand:VMUL 3 "register_operand" "w")))]
"TARGET_SIMD"
"<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]"
- [(set_attr "simd_type" "simd_<f>mul_elt")
- (set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
)
(define_insn "*aarch64_mul3_elt_<vswap_width_name><mode>"
@@ -550,9 +302,7 @@ (define_insn "*aarch64_mul3_elt_<vswap_w
(match_operand:VMUL_CHANGE_NLANES 3 "register_operand" "w")))]
"TARGET_SIMD"
"<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]"
- [(set_attr "simd_type" "simd_<f>mul_elt")
- (set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
)
(define_insn "*aarch64_mul3_elt_to_128df"
@@ -563,9 +313,7 @@ (define_insn "*aarch64_mul3_elt_to_128df
(match_operand:V2DF 1 "register_operand" "w")))]
"TARGET_SIMD"
"fmul\\t%0.2d, %1.2d, %2.d[0]"
- [(set_attr "simd_type" "simd_fmul_elt")
- (set_attr "type" "neon_fp_mul_d_scalar_q")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_mul_d_scalar_q")]
)
(define_insn "*aarch64_mul3_elt_to_64v2df"
@@ -577,9 +325,7 @@ (define_insn "*aarch64_mul3_elt_to_64v2d
(match_operand:DF 3 "register_operand" "w")))]
"TARGET_SIMD"
"fmul\\t%0.2d, %3.2d, %1.d[%2]"
- [(set_attr "simd_type" "simd_fmul_elt")
- (set_attr "type" "neon_fp_mul_d_scalar_q")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_mul_d_scalar_q")]
)
(define_insn "neg<mode>2"
@@ -587,9 +333,7 @@ (define_insn "neg<mode>2"
(neg:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
"TARGET_SIMD"
"neg\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_negabs")
- (set_attr "type" "neon_neg<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_neg<q>")]
)
(define_insn "abs<mode>2"
@@ -597,9 +341,7 @@ (define_insn "abs<mode>2"
(abs:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
"TARGET_SIMD"
"abs\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_negabs")
- (set_attr "type" "neon_abs<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_abs<q>")]
)
(define_insn "abd<mode>_3"
@@ -609,9 +351,7 @@ (define_insn "abd<mode>_3"
(match_operand:VDQ_BHSI 2 "register_operand" "w"))))]
"TARGET_SIMD"
"sabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_abd")
- (set_attr "type" "neon_abd<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_abd<q>")]
)
(define_insn "aba<mode>_3"
@@ -622,9 +362,7 @@ (define_insn "aba<mode>_3"
(match_operand:VDQ_BHSI 3 "register_operand" "0")))]
"TARGET_SIMD"
"saba\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_abd")
- (set_attr "type" "neon_arith_acc<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_arith_acc<q>")]
)
(define_insn "fabd<mode>_3"
@@ -634,9 +372,7 @@ (define_insn "fabd<mode>_3"
(match_operand:VDQF 2 "register_operand" "w"))))]
"TARGET_SIMD"
"fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fabd")
- (set_attr "type" "neon_fp_abd_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_abd_<Vetype><q>")]
)
(define_insn "*fabd_scalar<mode>3"
@@ -646,9 +382,7 @@ (define_insn "*fabd_scalar<mode>3"
(match_operand:GPF 2 "register_operand" "w"))))]
"TARGET_SIMD"
"fabd\t%<s>0, %<s>1, %<s>2"
- [(set_attr "simd_type" "simd_fabd")
- (set_attr "type" "neon_fp_abd_<Vetype><q>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_abd_<Vetype><q>")]
)
(define_insn "and<mode>3"
@@ -657,9 +391,7 @@ (define_insn "and<mode>3"
(match_operand:VDQ 2 "register_operand" "w")))]
"TARGET_SIMD"
"and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
- [(set_attr "simd_type" "simd_logic")
- (set_attr "type" "neon_logic<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_logic<q>")]
)
(define_insn "ior<mode>3"
@@ -668,9 +400,7 @@ (define_insn "ior<mode>3"
(match_operand:VDQ 2 "register_operand" "w")))]
"TARGET_SIMD"
"orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
- [(set_attr "simd_type" "simd_logic")
- (set_attr "type" "neon_logic<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_logic<q>")]
)
(define_insn "xor<mode>3"
@@ -679,9 +409,7 @@ (define_insn "xor<mode>3"
(match_operand:VDQ 2 "register_operand" "w")))]
"TARGET_SIMD"
"eor\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
- [(set_attr "simd_type" "simd_logic")
- (set_attr "type" "neon_logic<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_logic<q>")]
)
(define_insn "one_cmpl<mode>2"
@@ -689,9 +417,7 @@ (define_insn "one_cmpl<mode>2"
(not:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
"TARGET_SIMD"
"not\t%0.<Vbtype>, %1.<Vbtype>"
- [(set_attr "simd_type" "simd_logic")
- (set_attr "type" "neon_logic<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_logic<q>")]
)
(define_insn "aarch64_simd_vec_set<mode>"
@@ -705,9 +431,7 @@ (define_insn "aarch64_simd_vec_set<mode>
"@
ins\t%0.<Vetype>[%p2], %w1
ins\\t%0.<Vetype>[%p2], %1.<Vetype>[0]"
- [(set_attr "simd_type" "simd_insgp, simd_ins")
- (set_attr "type" "neon_from_gp<q>, neon_ins<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_from_gp<q>, neon_ins<q>")]
)
(define_insn "aarch64_simd_lshr<mode>"
@@ -716,9 +440,7 @@ (define_insn "aarch64_simd_lshr<mode>"
(match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))]
"TARGET_SIMD"
"ushr\t%0.<Vtype>, %1.<Vtype>, %2"
- [(set_attr "simd_type" "simd_shift_imm")
- (set_attr "type" "neon_shift_imm<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm<q>")]
)
(define_insn "aarch64_simd_ashr<mode>"
@@ -727,9 +449,7 @@ (define_insn "aarch64_simd_ashr<mode>"
(match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))]
"TARGET_SIMD"
"sshr\t%0.<Vtype>, %1.<Vtype>, %2"
- [(set_attr "simd_type" "simd_shift_imm")
- (set_attr "type" "neon_shift_imm<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm<q>")]
)
(define_insn "aarch64_simd_imm_shl<mode>"
@@ -738,9 +458,7 @@ (define_insn "aarch64_simd_imm_shl<mode>
(match_operand:VDQ 2 "aarch64_simd_lshift_imm" "Dl")))]
"TARGET_SIMD"
"shl\t%0.<Vtype>, %1.<Vtype>, %2"
- [(set_attr "simd_type" "simd_shift_imm")
- (set_attr "type" "neon_shift_imm<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm<q>")]
)
(define_insn "aarch64_simd_reg_sshl<mode>"
@@ -749,9 +467,7 @@ (define_insn "aarch64_simd_reg_sshl<mode
(match_operand:VDQ 2 "register_operand" "w")))]
"TARGET_SIMD"
"sshl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_shift")
- (set_attr "type" "neon_shift_reg<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_reg<q>")]
)
(define_insn "aarch64_simd_reg_shl<mode>_unsigned"
@@ -761,9 +477,7 @@ (define_insn "aarch64_simd_reg_shl<mode>
UNSPEC_ASHIFT_UNSIGNED))]
"TARGET_SIMD"
"ushl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_shift")
- (set_attr "type" "neon_shift_reg<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_reg<q>")]
)
(define_insn "aarch64_simd_reg_shl<mode>_signed"
@@ -773,9 +487,7 @@ (define_insn "aarch64_simd_reg_shl<mode>
UNSPEC_ASHIFT_SIGNED))]
"TARGET_SIMD"
"sshl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_shift")
- (set_attr "type" "neon_shift_reg<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_reg<q>")]
)
(define_expand "ashl<mode>3"
@@ -983,9 +695,7 @@ (define_insn "aarch64_simd_vec_setv2di"
"@
ins\t%0.d[%p2], %1
ins\\t%0.d[%p2], %1.d[0]"
- [(set_attr "simd_type" "simd_insgp, simd_ins")
- (set_attr "type" "neon_from_gp, neon_ins_q")
- (set_attr "simd_mode" "V2DI")]
+ [(set_attr "type" "neon_from_gp, neon_ins_q")]
)
(define_expand "vec_setv2di"
@@ -1010,9 +720,7 @@ (define_insn "aarch64_simd_vec_set<mode>
(match_operand:SI 2 "immediate_operand" "i")))]
"TARGET_SIMD"
"ins\t%0.<Vetype>[%p2], %1.<Vetype>[0]";
- [(set_attr "simd_type" "simd_ins")
- (set_attr "type" "neon_ins<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_ins<q>")]
)
(define_expand "vec_set<mode>"
@@ -1036,9 +744,7 @@ (define_insn "aarch64_mla<mode>"
(match_operand:VQ_S 1 "register_operand" "0")))]
"TARGET_SIMD"
"mla\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
- [(set_attr "simd_type" "simd_mla")
- (set_attr "type" "neon_mla_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype><q>")]
)
(define_insn "*aarch64_mla_elt<mode>"
@@ -1053,9 +759,7 @@ (define_insn "*aarch64_mla_elt<mode>"
(match_operand:VDQHS 4 "register_operand" "0")))]
"TARGET_SIMD"
"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
- [(set_attr "simd_type" "simd_mla")
- (set_attr "type" "neon_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
(define_insn "*aarch64_mla_elt_<vswap_width_name><mode>"
@@ -1070,9 +774,7 @@ (define_insn "*aarch64_mla_elt_<vswap_wi
(match_operand:VDQHS 4 "register_operand" "0")))]
"TARGET_SIMD"
"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
- [(set_attr "simd_type" "simd_mla")
- (set_attr "type" "neon_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
(define_insn "aarch64_mls<mode>"
@@ -1082,9 +784,7 @@ (define_insn "aarch64_mls<mode>"
(match_operand:VQ_S 3 "register_operand" "w"))))]
"TARGET_SIMD"
"mls\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
- [(set_attr "simd_type" "simd_mla")
- (set_attr "type" "neon_mla_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype><q>")]
)
(define_insn "*aarch64_mls_elt<mode>"
@@ -1099,9 +799,7 @@ (define_insn "*aarch64_mls_elt<mode>"
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
- [(set_attr "simd_type" "simd_mla")
- (set_attr "type" "neon_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
(define_insn "*aarch64_mls_elt_<vswap_width_name><mode>"
@@ -1116,9 +814,7 @@ (define_insn "*aarch64_mls_elt_<vswap_wi
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
- [(set_attr "simd_type" "simd_mla")
- (set_attr "type" "neon_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
;; Max/Min operations.
@@ -1128,9 +824,7 @@ (define_insn "<su><maxmin><mode>3"
(match_operand:VQ_S 2 "register_operand" "w")))]
"TARGET_SIMD"
"<su><maxmin>\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_minmax")
- (set_attr "type" "neon_minmax<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_minmax<q>")]
)
;; Move into low-half clearing high half to 0.
@@ -1145,10 +839,7 @@ (define_insn "move_lo_quad_<mode>"
dup\\t%d0, %1.d[0]
fmov\\t%d0, %1
dup\\t%d0, %1"
- [(set_attr "v8type" "*,fmov,*")
- (set_attr "type" "neon_dup<q>,fmov,neon_dup<q>")
- (set_attr "simd_type" "simd_dup,*,simd_dup")
- (set_attr "simd_mode" "<MODE>")
+ [(set_attr "type" "neon_dup<q>,fmov,neon_dup<q>")
(set_attr "simd" "yes,*,yes")
(set_attr "fp" "*,yes,*")
(set_attr "length" "4")]
@@ -1167,9 +858,7 @@ (define_insn "aarch64_simd_move_hi_quad_
"@
ins\\t%0.d[1], %1.d[0]
ins\\t%0.d[1], %1"
- [(set_attr "simd_type" "simd_ins,simd_ins")
- (set_attr "type" "neon_ins")
- (set_attr "simd_mode" "<MODE>")
+ [(set_attr "type" "neon_ins")
(set_attr "length" "4")]
)
@@ -1192,9 +881,7 @@ (define_insn "aarch64_simd_vec_pack_trun
(truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w")))]
"TARGET_SIMD"
"xtn\\t%0.<Vntype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_shiftn_imm")
- (set_attr "type" "neon_shift_imm_narrow_q")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm_narrow_q")]
)
(define_expand "vec_pack_trunc_<mode>"
@@ -1220,9 +907,7 @@ (define_insn "vec_pack_trunc_<mode>"
(truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w"))))]
"TARGET_SIMD"
"xtn\\t%0.<Vntype>, %1.<Vtype>\;xtn2\\t%0.<V2ntype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_shiftn2_imm")
- (set_attr "type" "multiple")
- (set_attr "simd_mode" "<MODE>")
+ [(set_attr "type" "multiple")
(set_attr "length" "8")]
)
@@ -1236,9 +921,7 @@ (define_insn "aarch64_simd_vec_unpack<su
)))]
"TARGET_SIMD"
"<su>shll %0.<Vwtype>, %1.<Vhalftype>, 0"
- [(set_attr "simd_type" "simd_shiftl_imm")
- (set_attr "type" "neon_shift_imm_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm_long")]
)
(define_insn "aarch64_simd_vec_unpack<su>_hi_<mode>"
@@ -1249,9 +932,7 @@ (define_insn "aarch64_simd_vec_unpack<su
)))]
"TARGET_SIMD"
"<su>shll2 %0.<Vwtype>, %1.<Vtype>, 0"
- [(set_attr "simd_type" "simd_shiftl_imm")
- (set_attr "type" "neon_shift_imm_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm_long")]
)
(define_expand "vec_unpack<su>_hi_<mode>"
@@ -1293,9 +974,7 @@ (define_insn "*aarch64_<su>mlal_lo<mode>
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
"<su>mlal\t%0.<Vwtype>, %2.<Vhalftype>, %4.<Vhalftype>"
- [(set_attr "simd_type" "simd_mlal")
- (set_attr "type" "neon_mla_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_long")]
)
(define_insn "*aarch64_<su>mlal_hi<mode>"
@@ -1311,9 +990,7 @@ (define_insn "*aarch64_<su>mlal_hi<mode>
(match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
"<su>mlal2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vtype>"
- [(set_attr "simd_type" "simd_mlal")
- (set_attr "type" "neon_mla_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_long")]
)
(define_insn "*aarch64_<su>mlsl_lo<mode>"
@@ -1329,9 +1006,7 @@ (define_insn "*aarch64_<su>mlsl_lo<mode>
(match_dup 3))))))]
"TARGET_SIMD"
"<su>mlsl\t%0.<Vwtype>, %2.<Vhalftype>, %4.<Vhalftype>"
- [(set_attr "simd_type" "simd_mlal")
- (set_attr "type" "neon_mla_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_long")]
)
(define_insn "*aarch64_<su>mlsl_hi<mode>"
@@ -1347,9 +1022,7 @@ (define_insn "*aarch64_<su>mlsl_hi<mode>
(match_dup 3))))))]
"TARGET_SIMD"
"<su>mlsl2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vtype>"
- [(set_attr "simd_type" "simd_mlal")
- (set_attr "type" "neon_mla_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_long")]
)
(define_insn "*aarch64_<su>mlal<mode>"
@@ -1363,9 +1036,7 @@ (define_insn "*aarch64_<su>mlal<mode>"
(match_operand:<VWIDE> 3 "register_operand" "0")))]
"TARGET_SIMD"
"<su>mlal\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_mlal")
- (set_attr "type" "neon_mla_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_long")]
)
(define_insn "*aarch64_<su>mlsl<mode>"
@@ -1379,9 +1050,7 @@ (define_insn "*aarch64_<su>mlsl<mode>"
(match_operand:VDW 3 "register_operand" "w")))))]
"TARGET_SIMD"
"<su>mlsl\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
- [(set_attr "simd_type" "simd_mlal")
- (set_attr "type" "neon_mla_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mla_<Vetype>_long")]
)
(define_insn "aarch64_simd_vec_<su>mult_lo_<mode>"
@@ -1394,9 +1063,7 @@ (define_insn "aarch64_simd_vec_<su>mult_
(match_dup 3)))))]
"TARGET_SIMD"
"<su>mull\\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>"
- [(set_attr "simd_type" "simd_mull")
- (set_attr "type" "neon_mul_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mul_<Vetype>_long")]
)
(define_expand "vec_widen_<su>mult_lo_<mode>"
@@ -1423,9 +1090,7 @@ (define_insn "aarch64_simd_vec_<su>mult_
(match_dup 3)))))]
"TARGET_SIMD"
"<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_mull")
- (set_attr "type" "neon_mul_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mul_<Vetype>_long")]
)
(define_expand "vec_widen_<su>mult_hi_<mode>"
@@ -1474,9 +1139,7 @@ (define_insn "add<mode>3"
(match_operand:VDQF 2 "register_operand" "w")))]
"TARGET_SIMD"
"fadd\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fadd")
- (set_attr "type" "neon_fp_addsub_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_addsub_<Vetype><q>")]
)
(define_insn "sub<mode>3"
@@ -1485,9 +1148,7 @@ (define_insn "sub<mode>3"
(match_operand:VDQF 2 "register_operand" "w")))]
"TARGET_SIMD"
"fsub\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fadd")
- (set_attr "type" "neon_fp_addsub_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_addsub_<Vetype><q>")]
)
(define_insn "mul<mode>3"
@@ -1496,9 +1157,7 @@ (define_insn "mul<mode>3"
(match_operand:VDQF 2 "register_operand" "w")))]
"TARGET_SIMD"
"fmul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fmul")
- (set_attr "type" "neon_fp_mul_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_mul_<Vetype><q>")]
)
(define_insn "div<mode>3"
@@ -1507,9 +1166,7 @@ (define_insn "div<mode>3"
(match_operand:VDQF 2 "register_operand" "w")))]
"TARGET_SIMD"
"fdiv\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fdiv")
- (set_attr "type" "neon_fp_div_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_div_<Vetype><q>")]
)
(define_insn "neg<mode>2"
@@ -1517,9 +1174,7 @@ (define_insn "neg<mode>2"
(neg:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
"TARGET_SIMD"
"fneg\\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_fnegabs")
- (set_attr "type" "neon_fp_neg_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_neg_<Vetype><q>")]
)
(define_insn "abs<mode>2"
@@ -1527,9 +1182,7 @@ (define_insn "abs<mode>2"
(abs:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
"TARGET_SIMD"
"fabs\\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_fnegabs")
- (set_attr "type" "neon_fp_abs_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_abs_<Vetype><q>")]
)
(define_insn "fma<mode>4"
@@ -1539,9 +1192,7 @@ (define_insn "fma<mode>4"
(match_operand:VDQF 3 "register_operand" "0")))]
"TARGET_SIMD"
"fmla\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fmla")
- (set_attr "type" "neon_fp_mla_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_mla_<Vetype><q>")]
)
(define_insn "*aarch64_fma4_elt<mode>"
@@ -1555,9 +1206,7 @@ (define_insn "*aarch64_fma4_elt<mode>"
(match_operand:VDQF 4 "register_operand" "0")))]
"TARGET_SIMD"
"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
- [(set_attr "simd_type" "simd_fmla_elt")
- (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
(define_insn "*aarch64_fma4_elt_<vswap_width_name><mode>"
@@ -1571,9 +1220,7 @@ (define_insn "*aarch64_fma4_elt_<vswap_w
(match_operand:VDQSF 4 "register_operand" "0")))]
"TARGET_SIMD"
"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
- [(set_attr "simd_type" "simd_fmla_elt")
- (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
(define_insn "*aarch64_fma4_elt_to_128df"
@@ -1585,9 +1232,7 @@ (define_insn "*aarch64_fma4_elt_to_128df
(match_operand:V2DF 3 "register_operand" "0")))]
"TARGET_SIMD"
"fmla\\t%0.2d, %2.2d, %1.2d[0]"
- [(set_attr "simd_type" "simd_fmla_elt")
- (set_attr "type" "neon_fp_mla_d_scalar_q")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
(define_insn "*aarch64_fma4_elt_to_64v2df"
@@ -1600,9 +1245,7 @@ (define_insn "*aarch64_fma4_elt_to_64v2d
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_SIMD"
"fmla\\t%0.2d, %3.2d, %1.2d[%2]"
- [(set_attr "simd_type" "simd_fmla_elt")
- (set_attr "type" "neon_fp_mla_d_scalar_q")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
(define_insn "fnma<mode>4"
@@ -1614,9 +1257,7 @@ (define_insn "fnma<mode>4"
(match_operand:VDQF 3 "register_operand" "0")))]
"TARGET_SIMD"
"fmls\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fmla")
- (set_attr "type" "neon_fp_mla_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_mla_<Vetype><q>")]
)
(define_insn "*aarch64_fnma4_elt<mode>"
@@ -1631,9 +1272,7 @@ (define_insn "*aarch64_fnma4_elt<mode>"
(match_operand:VDQF 4 "register_operand" "0")))]
"TARGET_SIMD"
"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
- [(set_attr "simd_type" "simd_fmla_elt")
- (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
(define_insn "*aarch64_fnma4_elt_<vswap_width_name><mode>"
@@ -1648,9 +1287,7 @@ (define_insn "*aarch64_fnma4_elt_<vswap_
(match_operand:VDQSF 4 "register_operand" "0")))]
"TARGET_SIMD"
"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
- [(set_attr "simd_type" "simd_fmla_elt")
- (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
(define_insn "*aarch64_fnma4_elt_to_128df"
@@ -1663,9 +1300,7 @@ (define_insn "*aarch64_fnma4_elt_to_128d
(match_operand:V2DF 3 "register_operand" "0")))]
"TARGET_SIMD"
"fmls\\t%0.2d, %2.2d, %1.2d[0]"
- [(set_attr "simd_type" "simd_fmla_elt")
- (set_attr "type" "neon_fp_mla_d_scalar_q")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
(define_insn "*aarch64_fnma4_elt_to_64v2df"
@@ -1679,9 +1314,7 @@ (define_insn "*aarch64_fnma4_elt_to_64v2
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_SIMD"
"fmls\\t%0.2d, %3.2d, %1.2d[%2]"
- [(set_attr "simd_type" "simd_fmla_elt")
- (set_attr "type" "neon_fp_mla_d_scalar_q")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
;; Vector versions of the floating-point frint patterns.
@@ -1692,9 +1325,7 @@ (define_insn "<frint_pattern><mode>2"
FRINT))]
"TARGET_SIMD"
"frint<frint_suffix>\\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_frint")
- (set_attr "type" "neon_fp_round_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_round_<Vetype><q>")]
)
;; Vector versions of the fcvt standard patterns.
@@ -1706,9 +1337,7 @@ (define_insn "l<fcvt_pattern><su_optab><
FCVT)))]
"TARGET_SIMD"
"fcvt<frint_suffix><su>\\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_fcvti")
- (set_attr "type" "neon_fp_to_int_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_to_int_<Vetype><q>")]
)
(define_expand "<optab><VDQF:mode><fcvt_target>2"
@@ -1740,9 +1369,7 @@ (define_insn "<optab><fcvt_target><VDQF:
(match_operand:<FCVT_TARGET> 1 "register_operand" "w")))]
"TARGET_SIMD"
"<su_optab>cvtf\\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_icvtf")
- (set_attr "type" "neon_int_to_fp_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_int_to_fp_<Vetype><q>")]
)
;; Conversions between vectors of floats and doubles.
@@ -1760,9 +1387,7 @@ (define_insn "vec_unpacks_lo_v4sf"
)))]
"TARGET_SIMD"
"fcvtl\\t%0.2d, %1.2s"
- [(set_attr "simd_type" "simd_fcvtl")
- (set_attr "type" "neon_fp_cvt_widen_s")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_cvt_widen_s")]
)
(define_insn "aarch64_float_extend_lo_v2df"
@@ -1771,9 +1396,7 @@ (define_insn "aarch64_float_extend_lo_v2
(match_operand:V2SF 1 "register_operand" "w")))]
"TARGET_SIMD"
"fcvtl\\t%0.2d, %1.2s"
- [(set_attr "simd_type" "simd_fcvtl")
- (set_attr "type" "neon_fp_cvt_widen_s")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_cvt_widen_s")]
)
(define_insn "vec_unpacks_hi_v4sf"
@@ -1785,9 +1408,7 @@ (define_insn "vec_unpacks_hi_v4sf"
)))]
"TARGET_SIMD"
"fcvtl2\\t%0.2d, %1.4s"
- [(set_attr "simd_type" "simd_fcvtl")
- (set_attr "type" "neon_fp_cvt_widen_s")
- (set_attr "simd_mode" "V2DF")]
+ [(set_attr "type" "neon_fp_cvt_widen_s")]
)
;; Float narrowing operations.
@@ -1798,9 +1419,7 @@ (define_insn "aarch64_float_truncate_lo_
(match_operand:V2DF 1 "register_operand" "w")))]
"TARGET_SIMD"
"fcvtn\\t%0.2s, %1.2d"
- [(set_attr "simd_type" "simd_fcvtl")
- (set_attr "type" "neon_fp_cvt_narrow_d_q")
- (set_attr "simd_mode" "V2SF")]
+ [(set_attr "type" "neon_fp_cvt_narrow_d_q")]
)
(define_insn "aarch64_float_truncate_hi_v4sf"
@@ -1811,9 +1430,7 @@ (define_insn "aarch64_float_truncate_hi_
(match_operand:V2DF 2 "register_operand" "w"))))]
"TARGET_SIMD"
"fcvtn2\\t%0.4s, %2.2d"
- [(set_attr "simd_type" "simd_fcvtl")
- (set_attr "type" "neon_fp_cvt_narrow_d_q")
- (set_attr "simd_mode" "V4SF")]
+ [(set_attr "type" "neon_fp_cvt_narrow_d_q")]
)
(define_expand "vec_pack_trunc_v2df"
@@ -1859,9 +1476,7 @@ (define_insn "aarch64_vmls<mode>"
(match_operand:VDQF 3 "register_operand" "w"))))]
"TARGET_SIMD"
"fmls\\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
- [(set_attr "simd_type" "simd_fmla")
- (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
;; FP Max/Min
@@ -1884,9 +1499,7 @@ (define_insn "<su><maxmin><mode>3"
(match_operand:VDQF 2 "register_operand" "w")))]
"TARGET_SIMD"
"f<maxmin>nm\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fminmax")
- (set_attr "type" "neon_fp_minmax_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_minmax_<Vetype><q>")]
)
(define_insn "<maxmin_uns><mode>3"
@@ -1896,9 +1509,7 @@ (define_insn "<maxmin_uns><mode>3"
FMAXMIN_UNS))]
"TARGET_SIMD"
"<maxmin_uns_op>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_fminmax")
- (set_attr "type" "neon_fp_minmax_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_minmax_<Vetype><q>")]
)
;; 'across lanes' add.
@@ -1909,9 +1520,7 @@ (define_insn "reduc_<sur>plus_<mode>"
SUADDV))]
"TARGET_SIMD"
"addv\\t%<Vetype>0, %1.<Vtype>"
- [(set_attr "simd_type" "simd_addv")
- (set_attr "type" "neon_reduc_add<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_reduc_add<q>")]
)
(define_insn "reduc_<sur>plus_v2di"
@@ -1920,9 +1529,7 @@ (define_insn "reduc_<sur>plus_v2di"
SUADDV))]
"TARGET_SIMD"
"addp\\t%d0, %1.2d"
- [(set_attr "simd_type" "simd_addv")
- (set_attr "type" "neon_reduc_add_q")
- (set_attr "simd_mode" "V2DI")]
+ [(set_attr "type" "neon_reduc_add_q")]
)
(define_insn "reduc_<sur>plus_v2si"
@@ -1931,9 +1538,7 @@ (define_insn "reduc_<sur>plus_v2si"
SUADDV))]
"TARGET_SIMD"
"addp\\t%0.2s, %1.2s, %1.2s"
- [(set_attr "simd_type" "simd_addv")
- (set_attr "type" "neon_reduc_add")
- (set_attr "simd_mode" "V2SI")]
+ [(set_attr "type" "neon_reduc_add")]
)
(define_insn "reduc_<sur>plus_<mode>"
@@ -1942,9 +1547,7 @@ (define_insn "reduc_<sur>plus_<mode>"
SUADDV))]
"TARGET_SIMD"
"faddp\\t%<Vetype>0, %1.<Vtype>"
- [(set_attr "simd_type" "simd_fadd")
- (set_attr "type" "neon_fp_reduc_add_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_reduc_add_<Vetype><q>")]
)
(define_insn "aarch64_addpv4sf"
@@ -1953,9 +1556,7 @@ (define_insn "aarch64_addpv4sf"
UNSPEC_FADDV))]
"TARGET_SIMD"
"faddp\\t%0.4s, %1.4s, %1.4s"
- [(set_attr "simd_type" "simd_fadd")
- (set_attr "type" "neon_fp_reduc_add_s_q")
- (set_attr "simd_mode" "V4SF")]
+ [(set_attr "type" "neon_fp_reduc_add_s_q")]
)
(define_expand "reduc_<sur>plus_v4sf"
@@ -1975,9 +1576,7 @@ (define_insn "clz<mode>2"
(clz:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w")))]
"TARGET_SIMD"
"clz\\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_cls")
- (set_attr "type" "neon_cls<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_cls<q>")]
)
;; 'across lanes' max and min ops.
@@ -1988,9 +1587,7 @@ (define_insn "reduc_<maxmin_uns>_<mode>"
MAXMINV))]
"TARGET_SIMD"
"<maxmin_uns_op>v\\t%<Vetype>0, %1.<Vtype>"
- [(set_attr "simd_type" "simd_minmaxv")
- (set_attr "type" "neon_reduc_minmax<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_reduc_minmax<q>")]
)
(define_insn "reduc_<maxmin_uns>_v2di"
@@ -1999,9 +1596,7 @@ (define_insn "reduc_<maxmin_uns>_v2di"
MAXMINV))]
"TARGET_SIMD"
"<maxmin_uns_op>p\\t%d0, %1.2d"
- [(set_attr "simd_type" "simd_minmaxv")
- (set_attr "type" "neon_reduc_minmax_q")
- (set_attr "simd_mode" "V2DI")]
+ [(set_attr "type" "neon_reduc_minmax_q")]
)
(define_insn "reduc_<maxmin_uns>_v2si"
@@ -2010,9 +1605,7 @@ (define_insn "reduc_<maxmin_uns>_v2si"
MAXMINV))]
"TARGET_SIMD"
"<maxmin_uns_op>p\\t%0.2s, %1.2s, %1.2s"
- [(set_attr "simd_type" "simd_minmaxv")
- (set_attr "type" "neon_reduc_minmax")
- (set_attr "simd_mode" "V2SI")]
+ [(set_attr "type" "neon_reduc_minmax")]
)
(define_insn "reduc_<maxmin_uns>_<mode>"
@@ -2021,9 +1614,7 @@ (define_insn "reduc_<maxmin_uns>_<mode>"
FMAXMINV))]
"TARGET_SIMD"
"<maxmin_uns_op>p\\t%<Vetype>0, %1.<Vtype>"
- [(set_attr "simd_type" "simd_fminmaxv")
- (set_attr "type" "neon_fp_reduc_minmax_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_reduc_minmax_<Vetype><q>")]
)
(define_insn "reduc_<maxmin_uns>_v4sf"
@@ -2032,9 +1623,7 @@ (define_insn "reduc_<maxmin_uns>_v4sf"
FMAXMINV))]
"TARGET_SIMD"
"<maxmin_uns_op>v\\t%s0, %1.4s"
- [(set_attr "simd_type" "simd_fminmaxv")
- (set_attr "type" "neon_fp_reduc_minmax_s_q")
- (set_attr "simd_mode" "V4SF")]
+ [(set_attr "type" "neon_fp_reduc_minmax_s_q")]
)
;; aarch64_simd_bsl may compile to any of bsl/bif/bit depending on register
@@ -2069,8 +1658,7 @@ (define_insn "aarch64_simd_bsl<mode>_int
bsl\\t%0.<Vbtype>, %2.<Vbtype>, %3.<Vbtype>
bit\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>
bif\\t%0.<Vbtype>, %3.<Vbtype>, %1.<Vbtype>"
- [(set_attr "simd_mode" "<MODE>")
- (set_attr "type" "neon_bsl<q>")]
+ [(set_attr "type" "neon_bsl<q>")]
)
(define_expand "aarch64_simd_bsl<mode>"
@@ -2435,9 +2023,7 @@ (define_insn "*aarch64_get_lane_extend<G
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
"smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]"
- [(set_attr "simd_type" "simd_movgp")
- (set_attr "type" "neon_to_gp<q>")
- (set_attr "simd_mode" "<VDQQH:MODE>")]
+ [(set_attr "type" "neon_to_gp<q>")]
)
(define_insn "*aarch64_get_lane_zero_extendsi<mode>"
@@ -2448,9 +2034,7 @@ (define_insn "*aarch64_get_lane_zero_ext
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
"umov\\t%w0, %1.<Vetype>[%2]"
- [(set_attr "simd_type" "simd_movgp")
- (set_attr "type" "neon_to_gp<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_to_gp<q>")]
)
;; Lane extraction of a value, neither sign nor zero extension
@@ -2464,9 +2048,7 @@ (define_insn "aarch64_get_lane<mode>"
"@
umov\\t%<vwcore>0, %1.<Vetype>[%2]
dup\\t%<Vetype>0, %1.<Vetype>[%2]"
- [(set_attr "simd_type" "simd_movgp, simd_dup")
- (set_attr "type" "neon_to_gp<q>, neon_dup<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_to_gp<q>, neon_dup<q>")]
)
(define_expand "aarch64_get_lanedi"
@@ -2589,9 +2171,7 @@ (define_insn "*aarch64_combinez<mode>"
(match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz")))]
"TARGET_SIMD"
"mov\\t%0.8b, %1.8b"
- [(set_attr "simd_type" "simd_move")
- (set_attr "type" "neon_move<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_move<q>")]
)
(define_insn_and_split "aarch64_combine<mode>"
@@ -2634,9 +2214,7 @@ (define_insn "aarch64_<ANY_EXTEND:su><AD
(match_dup 3)))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>l2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_addl")
- (set_attr "type" "neon_<ADDSUB:optab>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<ADDSUB:optab>_long")]
)
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_lo_internal"
@@ -2649,9 +2227,7 @@ (define_insn "aarch64_<ANY_EXTEND:su><AD
(match_dup 3)))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>l\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>"
- [(set_attr "simd_type" "simd_addl")
- (set_attr "type" "neon_<ADDSUB:optab>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<ADDSUB:optab>_long")]
)
@@ -2711,9 +2287,7 @@ (define_insn "aarch64_<ANY_EXTEND:su><AD
(match_operand:VDW 2 "register_operand" "w"))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>l %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_addl")
- (set_attr "type" "neon_<ADDSUB:optab>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<ADDSUB:optab>_long")]
)
;; <su><addsub>w<q>.
@@ -2725,9 +2299,7 @@ (define_insn "aarch64_<ANY_EXTEND:su><AD
(match_operand:VDW 2 "register_operand" "w"))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_addl")
- (set_attr "type" "neon_<ADDSUB:optab>_widen")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<ADDSUB:optab>_widen")]
)
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal"
@@ -2739,9 +2311,7 @@ (define_insn "aarch64_<ANY_EXTEND:su><AD
(match_operand:VQW 3 "vect_par_cnst_hi_half" "")))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_addl")
- (set_attr "type" "neon_<ADDSUB:optab>_widen")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<ADDSUB:optab>_widen")]
)
(define_expand "aarch64_saddw2<mode>"
@@ -2802,9 +2372,7 @@ (define_insn "aarch64_<sur>h<addsub><mod
HADDSUB))]
"TARGET_SIMD"
"<sur>h<addsub>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_add")
- (set_attr "type" "neon_<addsub>_halve<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<addsub>_halve<q>")]
)
;; <r><addsub>hn<q>.
@@ -2816,9 +2384,7 @@ (define_insn "aarch64_<sur><addsub>hn<mo
ADDSUBHN))]
"TARGET_SIMD"
"<sur><addsub>hn\\t%0.<Vntype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_addn")
- (set_attr "type" "neon_<addsub>_halve_narrow_q")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<addsub>_halve_narrow_q")]
)
(define_insn "aarch64_<sur><addsub>hn2<mode>"
@@ -2829,9 +2395,7 @@ (define_insn "aarch64_<sur><addsub>hn2<m
ADDSUBHN2))]
"TARGET_SIMD"
"<sur><addsub>hn2\\t%0.<V2ntype>, %2.<Vtype>, %3.<Vtype>"
- [(set_attr "simd_type" "simd_addn2")
- (set_attr "type" "neon_<addsub>_halve_narrow_q")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<addsub>_halve_narrow_q")]
)
;; pmul.
@@ -2843,9 +2407,7 @@ (define_insn "aarch64_pmul<mode>"
UNSPEC_PMUL))]
"TARGET_SIMD"
"pmul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_mul")
- (set_attr "type" "neon_mul_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_mul_<Vetype><q>")]
)
;; <su>q<addsub>
@@ -2856,9 +2418,7 @@ (define_insn "aarch64_<su_optab><optab><
(match_operand:VSDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"<su_optab><optab>\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
- [(set_attr "simd_type" "simd_add")
- (set_attr "type" "neon_<optab><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<optab><q>")]
)
;; suqadd and usqadd
@@ -2870,9 +2430,7 @@ (define_insn "aarch64_<sur>qadd<mode>"
USSUQADD))]
"TARGET_SIMD"
"<sur>qadd\\t%<v>0<Vmtype>, %<v>2<Vmtype>"
- [(set_attr "simd_type" "simd_sat_add")
- (set_attr "type" "neon_qadd<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_qadd<q>")]
)
;; sqmovun
@@ -2883,9 +2441,7 @@ (define_insn "aarch64_sqmovun<mode>"
UNSPEC_SQXTUN))]
"TARGET_SIMD"
"sqxtun\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>"
- [(set_attr "simd_type" "simd_sat_shiftn_imm")
- (set_attr "type" "neon_sat_shift_imm_narrow_q")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_shift_imm_narrow_q")]
)
;; sqmovn and uqmovn
@@ -2896,9 +2452,7 @@ (define_insn "aarch64_<sur>qmovn<mode>"
SUQMOVN))]
"TARGET_SIMD"
"<sur>qxtn\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>"
- [(set_attr "simd_type" "simd_sat_shiftn_imm")
- (set_attr "type" "neon_sat_shift_imm_narrow_q")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_shift_imm_narrow_q")]
)
;; <su>q<absneg>
@@ -2909,9 +2463,7 @@ (define_insn "aarch64_s<optab><mode>"
(match_operand:VSDQ_I_BHSI 1 "register_operand" "w")))]
"TARGET_SIMD"
"s<optab>\\t%<v>0<Vmtype>, %<v>1<Vmtype>"
- [(set_attr "simd_type" "simd_sat_negabs")
- (set_attr "type" "neon_<optab><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_<optab><q>")]
)
;; sq<r>dmulh.
@@ -2924,9 +2476,7 @@ (define_insn "aarch64_sq<r>dmulh<mode>"
VQDMULH))]
"TARGET_SIMD"
"sq<r>dmulh\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype><q>")]
)
;; sq<r>dmulh_lane
@@ -2943,9 +2493,7 @@ (define_insn "aarch64_sq<r>dmulh_lane<mo
"*
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
(define_insn "aarch64_sq<r>dmulh_laneq<mode>"
@@ -2960,9 +2508,7 @@ (define_insn "aarch64_sq<r>dmulh_laneq<m
"*
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
(define_insn "aarch64_sq<r>dmulh_lane<mode>"
@@ -2977,9 +2523,7 @@ (define_insn "aarch64_sq<r>dmulh_lane<mo
"*
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
;; vqdml[sa]l
@@ -2997,9 +2541,7 @@ (define_insn "aarch64_sqdml<SBINQOPS:as>
(const_int 1))))]
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>"
- [(set_attr "simd_type" "simd_sat_mlal")
- (set_attr "type" "neon_sat_mla_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mla_<Vetype>_long")]
)
;; vqdml[sa]l_lane
@@ -3021,9 +2563,7 @@ (define_insn "aarch64_sqdml<SBINQOPS:as>
(const_int 1))))]
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
- [(set_attr "simd_type" "simd_sat_mlal")
- (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
(define_insn "aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal"
@@ -3042,9 +2582,7 @@ (define_insn "aarch64_sqdml<SBINQOPS:as>
(const_int 1))))]
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
- [(set_attr "simd_type" "simd_sat_mlal")
- (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
(define_expand "aarch64_sqdmlal_lane<mode>"
@@ -3123,9 +2661,7 @@ (define_insn "aarch64_sqdml<SBINQOPS:as>
(const_int 1))))]
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]"
- [(set_attr "simd_type" "simd_sat_mlal")
- (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
;; sqdml[as]l2
@@ -3147,9 +2683,7 @@ (define_insn "aarch64_sqdml<SBINQOPS:as>
(const_int 1))))]
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>"
- [(set_attr "simd_type" "simd_sat_mlal")
- (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
(define_expand "aarch64_sqdmlal2<mode>"
@@ -3199,9 +2733,7 @@ (define_insn "aarch64_sqdml<SBINQOPS:as>
(const_int 1))))]
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
- [(set_attr "simd_type" "simd_sat_mlal")
- (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
(define_expand "aarch64_sqdmlal2_lane<mode>"
@@ -3284,9 +2816,7 @@ (define_insn "aarch64_sqdml<SBINQOPS:as>
(const_int 1))))]
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]"
- [(set_attr "simd_type" "simd_sat_mlal")
- (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
(define_expand "aarch64_sqdmlal2_n<mode>"
@@ -3330,9 +2860,7 @@ (define_insn "aarch64_sqdmull<mode>"
(const_int 1)))]
"TARGET_SIMD"
"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_long")]
)
;; vqdmull_lane
@@ -3352,9 +2880,7 @@ (define_insn "aarch64_sqdmull_lane<mode>
(const_int 1)))]
"TARGET_SIMD"
"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
(define_insn "aarch64_sqdmull_lane<mode>_internal"
@@ -3371,9 +2897,7 @@ (define_insn "aarch64_sqdmull_lane<mode>
(const_int 1)))]
"TARGET_SIMD"
"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
(define_expand "aarch64_sqdmull_lane<mode>"
@@ -3417,9 +2941,7 @@ (define_insn "aarch64_sqdmull_n<mode>"
(const_int 1)))]
"TARGET_SIMD"
"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[0]"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
;; vqdmull2
@@ -3442,9 +2964,7 @@ (define_insn "aarch64_sqdmull2<mode>_int
(const_int 1)))]
"TARGET_SIMD"
"sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
(define_expand "aarch64_sqdmull2<mode>"
@@ -3478,9 +2998,7 @@ (define_insn "aarch64_sqdmull2_lane<mode
(const_int 1)))]
"TARGET_SIMD"
"sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
(define_expand "aarch64_sqdmull2_lane<mode>"
@@ -3530,9 +3048,7 @@ (define_insn "aarch64_sqdmull2_n<mode>_i
(const_int 1)))]
"TARGET_SIMD"
"sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[0]"
- [(set_attr "simd_type" "simd_sat_mul")
- (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
(define_expand "aarch64_sqdmull2_n<mode>"
@@ -3557,9 +3073,7 @@ (define_insn "aarch64_<sur>shl<mode>"
VSHL))]
"TARGET_SIMD"
"<sur>shl\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>";
- [(set_attr "simd_type" "simd_shift")
- (set_attr "type" "neon_shift_reg<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_reg<q>")]
)
@@ -3573,9 +3087,7 @@ (define_insn "aarch64_<sur>q<r>shl<mode>
VQSHL))]
"TARGET_SIMD"
"<sur>q<r>shl\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>";
- [(set_attr "simd_type" "simd_sat_shift")
- (set_attr "type" "neon_sat_shift_reg<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_shift_reg<q>")]
)
;; vshll_n
@@ -3596,9 +3108,7 @@ (define_insn "aarch64_<sur>shll_n<mode>"
else {
return \"<sur>shll\\t%0.<Vwtype>, %1.<Vtype>, %2\";
}"
- [(set_attr "simd_type" "simd_shift_imm")
- (set_attr "type" "neon_shift_imm_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm_long")]
)
;; vshll_high_n
@@ -3619,9 +3129,7 @@ (define_insn "aarch64_<sur>shll2_n<mode>
else {
return \"<sur>shll2\\t%0.<Vwtype>, %1.<Vtype>, %2\";
}"
- [(set_attr "simd_type" "simd_shift_imm")
- (set_attr "type" "neon_shift_imm_long")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm_long")]
)
;; vrshr_n
@@ -3636,9 +3144,7 @@ (define_insn "aarch64_<sur>shr_n<mode>"
int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
aarch64_simd_const_bounds (operands[2], 1, bit_width + 1);
return \"<sur>shr\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2\";"
- [(set_attr "simd_type" "simd_shift_imm")
- (set_attr "type" "neon_sat_shift_imm<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_shift_imm<q>")]
)
;; v(r)sra_n
@@ -3654,9 +3160,7 @@ (define_insn "aarch64_<sur>sra_n<mode>"
int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
aarch64_simd_const_bounds (operands[3], 1, bit_width + 1);
return \"<sur>sra\\t%<v>0<Vmtype>, %<v>2<Vmtype>, %3\";"
- [(set_attr "simd_type" "simd_shift_imm_acc")
- (set_attr "type" "neon_shift_acc<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_acc<q>")]
)
;; vs<lr>i_n
@@ -3673,9 +3177,7 @@ (define_insn "aarch64_<sur>s<lr>i_n<mode
aarch64_simd_const_bounds (operands[3], 1 - <VSLRI:offsetlr>,
bit_width - <VSLRI:offsetlr> + 1);
return \"s<lr>i\\t%<v>0<Vmtype>, %<v>2<Vmtype>, %3\";"
- [(set_attr "simd_type" "simd_shift_imm")
- (set_attr "type" "neon_shift_imm<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_shift_imm<q>")]
)
;; vqshl(u)
@@ -3690,9 +3192,7 @@ (define_insn "aarch64_<sur>qshl<u>_n<mod
int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
aarch64_simd_const_bounds (operands[2], 0, bit_width);
return \"<sur>qshl<u>\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2\";"
- [(set_attr "simd_type" "simd_sat_shift_imm")
- (set_attr "type" "neon_sat_shift_imm<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_shift_imm<q>")]
)
@@ -3708,9 +3208,7 @@ (define_insn "aarch64_<sur>q<r>shr<u>n_n
int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
aarch64_simd_const_bounds (operands[2], 1, bit_width + 1);
return \"<sur>q<r>shr<u>n\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2\";"
- [(set_attr "simd_type" "simd_sat_shiftn_imm")
- (set_attr "type" "neon_sat_shift_imm_narrow_q")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_sat_shift_imm_narrow_q")]
)
@@ -3729,9 +3227,7 @@ (define_insn "aarch64_cm<optab><mode>"
"@
cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
cm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"
- [(set_attr "simd_type" "simd_cmp")
- (set_attr "type" "neon_compare<q>, neon_compare_zero<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_compare<q>, neon_compare_zero<q>")]
)
(define_insn_and_split "aarch64_cm<optab>di"
@@ -3760,9 +3256,7 @@ (define_insn_and_split "aarch64_cm<optab
emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
DONE;
}
- [(set_attr "simd_type" "simd_cmp")
- (set_attr "type" "neon_compare, neon_compare_zero, multiple")
- (set_attr "simd_mode" "DI")]
+ [(set_attr "type" "neon_compare, neon_compare_zero, multiple")]
)
;; cm(hs|hi)
@@ -3776,9 +3270,7 @@ (define_insn "aarch64_cm<optab><mode>"
)))]
"TARGET_SIMD"
"cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
- [(set_attr "simd_type" "simd_cmp")
- (set_attr "type" "neon_compare<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_compare<q>")]
)
(define_insn_and_split "aarch64_cm<optab>di"
@@ -3806,9 +3298,7 @@ (define_insn_and_split "aarch64_cm<optab
emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
DONE;
}
- [(set_attr "simd_type" "simd_cmp")
- (set_attr "type" "neon_compare, neon_compare_zero")
- (set_attr "simd_mode" "DI")]
+ [(set_attr "type" "neon_compare, neon_compare_zero")]
)
;; cmtst
@@ -3823,9 +3313,7 @@ (define_insn "aarch64_cmtst<mode>"
(vec_duplicate:<V_cmp_result> (const_int 0)))))]
"TARGET_SIMD"
"cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
- [(set_attr "simd_type" "simd_cmp")
- (set_attr "type" "neon_tst<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_tst<q>")]
)
(define_insn_and_split "aarch64_cmtstdi"
@@ -3855,9 +3343,7 @@ (define_insn_and_split "aarch64_cmtstdi"
emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
DONE;
}
- [(set_attr "simd_type" "simd_cmp")
- (set_attr "type" "neon_tst")
- (set_attr "simd_mode" "DI")]
+ [(set_attr "type" "neon_tst")]
)
;; fcm(eq|ge|gt|le|lt)
@@ -3873,9 +3359,7 @@ (define_insn "aarch64_cm<optab><mode>"
"@
fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
- [(set_attr "simd_type" "simd_fcmp")
- (set_attr "type" "neon_fp_compare_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_compare_<Vetype><q>")]
)
;; fac(ge|gt)
@@ -3891,9 +3375,7 @@ (define_insn "*aarch64_fac<optab><mode>"
)))]
"TARGET_SIMD"
"fac<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
- [(set_attr "simd_type" "simd_fcmp")
- (set_attr "type" "neon_fp_compare_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_compare_<Vetype><q>")]
)
;; addp
@@ -3906,9 +3388,7 @@ (define_insn "aarch64_addp<mode>"
UNSPEC_ADDP))]
"TARGET_SIMD"
"addp\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
- [(set_attr "simd_type" "simd_add")
- (set_attr "type" "neon_reduc_add<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_reduc_add<q>")]
)
(define_insn "aarch64_addpdi"
@@ -3918,9 +3398,7 @@ (define_insn "aarch64_addpdi"
UNSPEC_ADDP))]
"TARGET_SIMD"
"addp\t%d0, %1.2d"
- [(set_attr "simd_type" "simd_add")
- (set_attr "type" "neon_reduc_add")
- (set_attr "simd_mode" "DI")]
+ [(set_attr "type" "neon_reduc_add")]
)
;; sqrt
@@ -3930,9 +3408,7 @@ (define_insn "sqrt<mode>2"
(sqrt:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
"TARGET_SIMD"
"fsqrt\\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_fsqrt")
- (set_attr "type" "neon_fp_sqrt_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_sqrt_<Vetype><q>")]
)
;; Patterns for vector struct loads and stores.
@@ -3944,9 +3420,8 @@ (define_insn "vec_load_lanesoi<mode>"
UNSPEC_LD2))]
"TARGET_SIMD"
"ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
- [(set_attr "simd_type" "simd_load2")
- (set_attr "type" "neon_load2_2reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load2_2reg<q>")]
+)
(define_insn "vec_store_lanesoi<mode>"
[(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
@@ -3955,9 +3430,8 @@ (define_insn "vec_store_lanesoi<mode>"
UNSPEC_ST2))]
"TARGET_SIMD"
"st2\\t{%S1.<Vtype> - %T1.<Vtype>}, %0"
- [(set_attr "simd_type" "simd_store2")
- (set_attr "type" "neon_store2_2reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store2_2reg<q>")]
+)
(define_insn "vec_load_lanesci<mode>"
[(set (match_operand:CI 0 "register_operand" "=w")
@@ -3966,9 +3440,8 @@ (define_insn "vec_load_lanesci<mode>"
UNSPEC_LD3))]
"TARGET_SIMD"
"ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
- [(set_attr "simd_type" "simd_load3")
- (set_attr "type" "neon_load3_3reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load3_3reg<q>")]
+)
(define_insn "vec_store_lanesci<mode>"
[(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv")
@@ -3977,9 +3450,8 @@ (define_insn "vec_store_lanesci<mode>"
UNSPEC_ST3))]
"TARGET_SIMD"
"st3\\t{%S1.<Vtype> - %U1.<Vtype>}, %0"
- [(set_attr "simd_type" "simd_store3")
- (set_attr "type" "neon_store3_3reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store3_3reg<q>")]
+)
(define_insn "vec_load_lanesxi<mode>"
[(set (match_operand:XI 0 "register_operand" "=w")
@@ -3988,9 +3460,8 @@ (define_insn "vec_load_lanesxi<mode>"
UNSPEC_LD4))]
"TARGET_SIMD"
"ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
- [(set_attr "simd_type" "simd_load4")
- (set_attr "type" "neon_load4_4reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load4_4reg<q>")]
+)
(define_insn "vec_store_lanesxi<mode>"
[(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv")
@@ -3999,9 +3470,8 @@ (define_insn "vec_store_lanesxi<mode>"
UNSPEC_ST4))]
"TARGET_SIMD"
"st4\\t{%S1.<Vtype> - %V1.<Vtype>}, %0"
- [(set_attr "simd_type" "simd_store4")
- (set_attr "type" "neon_store4_4reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store4_4reg<q>")]
+)
;; Reload patterns for AdvSIMD register list operands.
@@ -4033,11 +3503,10 @@ (define_insn "*aarch64_mov<mode>"
default: gcc_unreachable ();
}
}
- [(set_attr "simd_type" "simd_move,simd_store<nregs>,simd_load<nregs>")
- (set_attr "type" "neon_move,neon_store<nregs>_<nregs>reg_q,\
+ [(set_attr "type" "neon_move,neon_store<nregs>_<nregs>reg_q,\
neon_load<nregs>_<nregs>reg_q")
- (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))
- (set_attr "simd_mode" "<MODE>")])
+ (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
+)
(define_split
[(set (match_operand:OI 0 "register_operand" "")
@@ -4119,9 +3588,8 @@ (define_insn "aarch64_ld2<mode>_dreg"
(vec_duplicate:VD (const_int 0)))) 0))]
"TARGET_SIMD"
"ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
- [(set_attr "simd_type" "simd_load2")
- (set_attr "type" "neon_load2_2reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load2_2reg<q>")]
+)
(define_insn "aarch64_ld2<mode>_dreg"
[(set (match_operand:OI 0 "register_operand" "=w")
@@ -4137,9 +3605,8 @@ (define_insn "aarch64_ld2<mode>_dreg"
(const_int 0))) 0))]
"TARGET_SIMD"
"ld1\\t{%S0.1d - %T0.1d}, %1"
- [(set_attr "simd_type" "simd_load2")
- (set_attr "type" "neon_load1_2reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load1_2reg<q>")]
+)
(define_insn "aarch64_ld3<mode>_dreg"
[(set (match_operand:CI 0 "register_operand" "=w")
@@ -4160,9 +3627,8 @@ (define_insn "aarch64_ld3<mode>_dreg"
(vec_duplicate:VD (const_int 0)))) 0))]
"TARGET_SIMD"
"ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
- [(set_attr "simd_type" "simd_load3")
- (set_attr "type" "neon_load3_3reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load3_3reg<q>")]
+)
(define_insn "aarch64_ld3<mode>_dreg"
[(set (match_operand:CI 0 "register_operand" "=w")
@@ -4183,9 +3649,8 @@ (define_insn "aarch64_ld3<mode>_dreg"
(const_int 0))) 0))]
"TARGET_SIMD"
"ld1\\t{%S0.1d - %U0.1d}, %1"
- [(set_attr "simd_type" "simd_load3")
- (set_attr "type" "neon_load1_3reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load1_3reg<q>")]
+)
(define_insn "aarch64_ld4<mode>_dreg"
[(set (match_operand:XI 0 "register_operand" "=w")
@@ -4211,9 +3676,8 @@ (define_insn "aarch64_ld4<mode>_dreg"
(vec_duplicate:VD (const_int 0))))) 0))]
"TARGET_SIMD"
"ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
- [(set_attr "simd_type" "simd_load4")
- (set_attr "type" "neon_load4_4reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load4_4reg<q>")]
+)
(define_insn "aarch64_ld4<mode>_dreg"
[(set (match_operand:XI 0 "register_operand" "=w")
@@ -4239,9 +3703,8 @@ (define_insn "aarch64_ld4<mode>_dreg"
(const_int 0)))) 0))]
"TARGET_SIMD"
"ld1\\t{%S0.1d - %V0.1d}, %1"
- [(set_attr "simd_type" "simd_load4")
- (set_attr "type" "neon_load1_4reg<q>")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load1_4reg<q>")]
+)
(define_expand "aarch64_ld<VSTRUCT:nregs><VDC:mode>"
[(match_operand:VSTRUCT 0 "register_operand" "=w")
@@ -4355,9 +3818,7 @@ (define_insn "aarch64_tbl1<mode>"
UNSPEC_TBL))]
"TARGET_SIMD"
"tbl\\t%0.<Vtype>, {%1.16b}, %2.<Vtype>"
- [(set_attr "simd_type" "simd_tbl")
- (set_attr "type" "neon_tbl1<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_tbl1<q>")]
)
;; Two source registers.
@@ -4369,9 +3830,7 @@ (define_insn "aarch64_tbl2v16qi"
UNSPEC_TBL))]
"TARGET_SIMD"
"tbl\\t%0.16b, {%S1.16b - %T1.16b}, %2.16b"
- [(set_attr "simd_type" "simd_tbl")
- (set_attr "type" "neon_tbl2_q")
- (set_attr "simd_mode" "V16QI")]
+ [(set_attr "type" "neon_tbl2_q")]
)
(define_insn_and_split "aarch64_combinev16qi"
@@ -4397,9 +3856,7 @@ (define_insn "aarch64_<PERMUTE:perm_insn
PERMUTE))]
"TARGET_SIMD"
"<PERMUTE:perm_insn><PERMUTE:perm_hilo>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
- [(set_attr "simd_type" "simd_<PERMUTE:perm_insn>")
- (set_attr "type" "neon_permute<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_permute<q>")]
)
(define_insn "aarch64_st2<mode>_dreg"
@@ -4409,9 +3866,8 @@ (define_insn "aarch64_st2<mode>_dreg"
UNSPEC_ST2))]
"TARGET_SIMD"
"st2\\t{%S1.<Vtype> - %T1.<Vtype>}, %0"
- [(set_attr "simd_type" "simd_store2")
- (set_attr "type" "neon_store2_2reg")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store2_2reg")]
+)
(define_insn "aarch64_st2<mode>_dreg"
[(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv")
@@ -4420,9 +3876,8 @@ (define_insn "aarch64_st2<mode>_dreg"
UNSPEC_ST2))]
"TARGET_SIMD"
"st1\\t{%S1.1d - %T1.1d}, %0"
- [(set_attr "simd_type" "simd_store2")
- (set_attr "type" "neon_store1_2reg")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store1_2reg")]
+)
(define_insn "aarch64_st3<mode>_dreg"
[(set (match_operand:EI 0 "aarch64_simd_struct_operand" "=Utv")
@@ -4431,9 +3886,8 @@ (define_insn "aarch64_st3<mode>_dreg"
UNSPEC_ST3))]
"TARGET_SIMD"
"st3\\t{%S1.<Vtype> - %U1.<Vtype>}, %0"
- [(set_attr "simd_type" "simd_store3")
- (set_attr "type" "neon_store3_3reg")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store3_3reg")]
+)
(define_insn "aarch64_st3<mode>_dreg"
[(set (match_operand:EI 0 "aarch64_simd_struct_operand" "=Utv")
@@ -4442,9 +3896,8 @@ (define_insn "aarch64_st3<mode>_dreg"
UNSPEC_ST3))]
"TARGET_SIMD"
"st1\\t{%S1.1d - %U1.1d}, %0"
- [(set_attr "simd_type" "simd_store3")
- (set_attr "type" "neon_store1_3reg")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store1_3reg")]
+)
(define_insn "aarch64_st4<mode>_dreg"
[(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
@@ -4453,9 +3906,8 @@ (define_insn "aarch64_st4<mode>_dreg"
UNSPEC_ST4))]
"TARGET_SIMD"
"st4\\t{%S1.<Vtype> - %V1.<Vtype>}, %0"
- [(set_attr "simd_type" "simd_store4")
- (set_attr "type" "neon_store4_4reg")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store4_4reg")]
+)
(define_insn "aarch64_st4<mode>_dreg"
[(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
@@ -4464,9 +3916,8 @@ (define_insn "aarch64_st4<mode>_dreg"
UNSPEC_ST4))]
"TARGET_SIMD"
"st1\\t{%S1.1d - %V1.1d}, %0"
- [(set_attr "simd_type" "simd_store4")
- (set_attr "type" "neon_store1_4reg")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_store1_4reg")]
+)
(define_expand "aarch64_st<VSTRUCT:nregs><VDC:mode>"
[(match_operand:DI 0 "register_operand" "r")
@@ -4544,9 +3995,8 @@ (define_insn "*aarch64_simd_ld1r<mode>"
(match_operand:<VEL> 1 "aarch64_simd_struct_operand" "Utv")))]
"TARGET_SIMD"
"ld1r\\t{%0.<Vtype>}, %1"
- [(set_attr "simd_type" "simd_load1r")
- (set_attr "type" "neon_load1_all_lanes")
- (set_attr "simd_mode" "<MODE>")])
+ [(set_attr "type" "neon_load1_all_lanes")]
+)
(define_insn "aarch64_frecpe<mode>"
[(set (match_operand:VDQF 0 "register_operand" "=w")
@@ -4554,9 +4004,7 @@ (define_insn "aarch64_frecpe<mode>"
UNSPEC_FRECPE))]
"TARGET_SIMD"
"frecpe\\t%0.<Vtype>, %1.<Vtype>"
- [(set_attr "simd_type" "simd_frecpe")
- (set_attr "type" "neon_fp_recpe_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_recpe_<Vetype><q>")]
)
(define_insn "aarch64_frecp<FRECP:frecp_suffix><mode>"
@@ -4565,9 +4013,7 @@ (define_insn "aarch64_frecp<FRECP:frecp_
FRECP))]
"TARGET_SIMD"
"frecp<FRECP:frecp_suffix>\\t%<s>0, %<s>1"
- [(set_attr "simd_type" "simd_frecp<FRECP:frecp_suffix>")
- (set_attr "type" "neon_fp_recp<FRECP:frecp_suffix>_<GPF:Vetype><GPF:q>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_recp<FRECP:frecp_suffix>_<GPF:Vetype><GPF:q>")]
)
(define_insn "aarch64_frecps<mode>"
@@ -4577,9 +4023,7 @@ (define_insn "aarch64_frecps<mode>"
UNSPEC_FRECPS))]
"TARGET_SIMD"
"frecps\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
- [(set_attr "simd_type" "simd_frecps")
- (set_attr "type" "neon_fp_recps_<Vetype><q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_fp_recps_<Vetype><q>")]
)
;; Standard pattern name vec_extract<mode>.
@@ -4594,7 +4038,6 @@ (define_insn "vec_extract<mode>"
umov\\t%<vw>0, %1.<Vetype>[%2]
dup\\t%<Vetype>0, %1.<Vetype>[%2]
st1\\t{%1.<Vetype>}[%2], %0"
- [(set_attr "simd_type" "simd_movgp, simd_dup, simd_store1s")
- (set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")
- (set_attr "simd_mode" "<MODE>")]
+ [(set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")]
)
+
@@ -793,11 +793,10 @@ (define_insn "*mov<mode>_aarch64"
}
}
[(set_attr "v8type" "move,alu,alu,load1,load1,store1,store1,*,*,*")
- (set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,*,*,*")
- (set_attr "simd_type" "*,*,simd_move_imm,*,*,*,*,simd_movgp,simd_dupgp,simd_dup")
+ (set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
+ neon_from_gp<q>,neon_from_gp<q>, neon_dup")
(set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")
- (set_attr "mode" "<MODE>")
- (set_attr "simd_mode" "<MODE>")]
+ (set_attr "mode" "<MODE>")]
)
(define_expand "mov<mode>"
@@ -912,13 +911,13 @@ (define_insn "*movti_aarch64"
str\\t%q1, %0"
[(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \
load2,store2,store2,fpsimd_load,fpsimd_store")
- (set_attr "type" "multiple,f_mcr,f_mrc,*, \
+ (set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_q, \
load2,store2,store2,f_loadd,f_stored")
- (set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI")
(set_attr "length" "8,8,8,4,4,4,4,4,4")
- (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")
- (set_attr "simd" "*,*,*,yes,*,*,*,*,*")])
+ (set_attr "simd" "*,*,*,yes,*,*,*,*,*")
+ (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")]
+)
;; Split a TImode register-register or register-immediate move into
;; its component DImode pieces, taking care to handle overlapping
@@ -2119,11 +2118,9 @@ (define_insn "neg<mode>2"
neg\\t%<w>0, %<w>1
neg\\t%<rtn>0<vas>, %<rtn>1<vas>"
[(set_attr "v8type" "alu")
- (set_attr "type" "alu_reg")
- (set_attr "simd_type" "*,simd_negabs")
+ (set_attr "type" "alu_reg, neon_neg<q>")
(set_attr "simd" "*,yes")
- (set_attr "mode" "<MODE>")
- (set_attr "simd_mode" "<MODE>")]
+ (set_attr "mode" "<MODE>")]
)
;; zero_extend version of above
@@ -3203,10 +3200,8 @@ (define_insn "*aarch64_ashl_sisd_or_int_
ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>
lsl\t%<w>0, %<w>1, %<w>2"
[(set_attr "simd" "yes,yes,no")
- (set_attr "simd_type" "simd_shift_imm,simd_shift,*")
- (set_attr "simd_mode" "<MODE>,<MODE>,*")
(set_attr "v8type" "*,*,shift")
- (set_attr "type" "*,*,shift_reg")
+ (set_attr "type" "neon_shift_imm<q>, neon_shift_reg<q>,shift_reg")
(set_attr "mode" "*,*,<MODE>")]
)
@@ -3222,10 +3217,8 @@ (define_insn "*aarch64_lshr_sisd_or_int_
#
lsr\t%<w>0, %<w>1, %<w>2"
[(set_attr "simd" "yes,yes,no")
- (set_attr "simd_type" "simd_shift_imm,simd_shift,*")
- (set_attr "simd_mode" "<MODE>,<MODE>,*")
(set_attr "v8type" "*,*,shift")
- (set_attr "type" "*,*,shift_reg")
+ (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")
(set_attr "mode" "*,*,<MODE>")]
)
@@ -3267,10 +3260,8 @@ (define_insn "*aarch64_ashr_sisd_or_int_
#
asr\t%<w>0, %<w>1, %<w>2"
[(set_attr "simd" "yes,yes,no")
- (set_attr "simd_type" "simd_shift_imm,simd_shift,*")
- (set_attr "simd_mode" "<MODE>,<MODE>,*")
(set_attr "v8type" "*,*,shift")
- (set_attr "type" "*,*,shift_reg")
+ (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")
(set_attr "mode" "*,*,<MODE>")]
)
@@ -3308,8 +3299,7 @@ (define_insn "*aarch64_sisd_ushl"
"TARGET_SIMD"
"ushl\t%d0, %d1, %d2"
[(set_attr "simd" "yes")
- (set_attr "simd_type" "simd_shift")
- (set_attr "simd_mode" "DI")]
+ (set_attr "type" "neon_shift_reg")]
)
(define_insn "*aarch64_ushl_2s"
@@ -3320,8 +3310,7 @@ (define_insn "*aarch64_ushl_2s"
"TARGET_SIMD"
"ushl\t%0.2s, %1.2s, %2.2s"
[(set_attr "simd" "yes")
- (set_attr "simd_type" "simd_shift")
- (set_attr "simd_mode" "DI")]
+ (set_attr "type" "neon_shift_reg")]
)
(define_insn "*aarch64_sisd_sshl"
@@ -3332,8 +3321,7 @@ (define_insn "*aarch64_sisd_sshl"
"TARGET_SIMD"
"sshl\t%d0, %d1, %d2"
[(set_attr "simd" "yes")
- (set_attr "simd_type" "simd_shift")
- (set_attr "simd_mode" "DI")]
+ (set_attr "type" "neon_shift_reg")]
)
(define_insn "*aarch64_sshl_2s"
@@ -3344,8 +3332,7 @@ (define_insn "*aarch64_sshl_2s"
"TARGET_SIMD"
"sshl\t%0.2s, %1.2s, %2.2s"
[(set_attr "simd" "yes")
- (set_attr "simd_type" "simd_shift")
- (set_attr "simd_mode" "DI")]
+ (set_attr "type" "neon_shift_reg")]
)
(define_insn "*aarch64_sisd_neg_qi"
@@ -3355,8 +3342,7 @@ (define_insn "*aarch64_sisd_neg_qi"
"TARGET_SIMD"
"neg\t%d0, %d1"
[(set_attr "simd" "yes")
- (set_attr "simd_type" "simd_negabs")
- (set_attr "simd_mode" "QI")]
+ (set_attr "type" "neon_neg")]
)
;; Rotate right