From patchwork Mon Nov 4 05:28:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 288108 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5697B2C0095 for ; Mon, 4 Nov 2013 16:28:15 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=eoc QY7pR78Hv1wRvawZDZqIA43kQJsnRx8fS5tptbUON8Ip3zncWPEbUsfJSR8l8Sal UGeUXGAXQZhPm9KsNY1sNYDx+vLhJHc7Z236QDg0n7j7qzhik18+bqJ/LVo2fXve C0xSuKuOSBFb5pX5moQE+Kq1Nhutl6ce1lJMTA4M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; s=default; bh=THV40S6b9 w60AoW8kfpa/tI1kOY=; b=Al2McV+ct/GZbR3KHEyLE88Cnbxl+R7wual1cC4ye Un4ZVCwHNJYAG9jXy3Pz0ur1y/BQf2kSjPJGeJe6M5+cUEncJX4STUg45Vd+d0yL 6KGf4PdTeyzsC3VBIuUcSAAvBZQmvGi3wQC4NC5+xZJ9t7ZIvg3VQchxKAu339uH ZM= Received: (qmail 9768 invoked by alias); 4 Nov 2013 05:28:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9758 invoked by uid 89); 4 Nov 2013 05:28:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_20, RDNS_NONE, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: e23smtp04.au.ibm.com Received: from Unknown (HELO e23smtp04.au.ibm.com) (202.81.31.146) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 04 Nov 2013 05:28:05 +0000 Received: from /spool/local by e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 4 Nov 2013 15:27:40 +1000 Received: from d23dlp01.au.ibm.com (202.81.31.203) by e23smtp04.au.ibm.com (202.81.31.210) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Mon, 4 Nov 2013 15:27:39 +1000 Received: from d23relay04.au.ibm.com (d23relay04.au.ibm.com [9.190.234.120]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id 8EFAE2CE8055 for ; Mon, 4 Nov 2013 16:27:38 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay04.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id rA45AAU58389078 for ; Mon, 4 Nov 2013 16:10:10 +1100 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id rA45Rb1b029814 for ; Mon, 4 Nov 2013 16:27:37 +1100 Received: from [9.65.200.189] (sig-9-65-200-189.mts.ibm.com [9.65.200.189]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id rA45RZQe029747; Mon, 4 Nov 2013 16:27:36 +1100 Message-ID: <1383542887.6275.299.camel@gnopaine> Subject: [PATCH, rs6000] (1/3) Reverse meanings of multiply even/odd for little endian From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com Date: Sun, 03 Nov 2013 23:28:07 -0600 Mime-Version: 1.0 X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13110405-9264-0000-0000-000004DC58EF X-IsSubscribed: yes Hi, This patch reverses the meanings of multiply even/odd instructions for little endian. Since these instructions use a big-endian idea of evenness/oddness, the nominal meanings of the instructions is wrong for little endian. Bootstrapped and tested with the rest of the patch set on powerpc64{,le}-unknown-linux-gnu with no regressions. Ok for trunk? Thanks, Bill 2013-11-03 Bill Schmidt * config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Swap meanings of even and odd multiplies for little endian. (vec_widen_smult_even_v16qi): Likewise. (vec_widen_umult_even_v8hi): Likewise. (vec_widen_smult_even_v8hi): Likewise. (vec_widen_umult_odd_v16qi): Likewise. (vec_widen_smult_odd_v16qi): Likewise. (vec_widen_umult_odd_v8hi): Likewise. (vec_widen_smult_odd_v8hi): Likewise. Index: gcc/config/rs6000/altivec.md =================================================================== --- gcc/config/rs6000/altivec.md (revision 204192) +++ gcc/config/rs6000/altivec.md (working copy) @@ -978,7 +988,12 @@ (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VMULEUB))] "TARGET_ALTIVEC" - "vmuleub %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmuleub %0,%1,%2"; + else + return "vmuloub %0,%1,%2"; +} [(set_attr "type" "veccomplex")]) (define_insn "vec_widen_smult_even_v16qi" @@ -987,7 +1002,12 @@ (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VMULESB))] "TARGET_ALTIVEC" - "vmulesb %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmulesb %0,%1,%2"; + else + return "vmulosb %0,%1,%2"; +} [(set_attr "type" "veccomplex")]) (define_insn "vec_widen_umult_even_v8hi" @@ -996,7 +1016,12 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMULEUH))] "TARGET_ALTIVEC" - "vmuleuh %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmuleuh %0,%1,%2"; + else + return "vmulouh %0,%1,%2"; +} [(set_attr "type" "veccomplex")]) (define_insn "vec_widen_smult_even_v8hi" @@ -1005,7 +1030,12 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMULESH))] "TARGET_ALTIVEC" - "vmulesh %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmulesh %0,%1,%2"; + else + return "vmulosh %0,%1,%2"; +} [(set_attr "type" "veccomplex")]) (define_insn "vec_widen_umult_odd_v16qi" @@ -1014,7 +1044,12 @@ (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VMULOUB))] "TARGET_ALTIVEC" - "vmuloub %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmuloub %0,%1,%2"; + else + return "vmuleub %0,%1,%2"; +} [(set_attr "type" "veccomplex")]) (define_insn "vec_widen_smult_odd_v16qi" @@ -1023,7 +1058,12 @@ (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VMULOSB))] "TARGET_ALTIVEC" - "vmulosb %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmulosb %0,%1,%2"; + else + return "vmulesb %0,%1,%2"; +} [(set_attr "type" "veccomplex")]) (define_insn "vec_widen_umult_odd_v8hi" @@ -1032,7 +1072,12 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMULOUH))] "TARGET_ALTIVEC" - "vmulouh %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmulouh %0,%1,%2"; + else + return "vmuleuh %0,%1,%2"; +} [(set_attr "type" "veccomplex")]) (define_insn "vec_widen_smult_odd_v8hi" @@ -1041,7 +1086,12 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMULOSH))] "TARGET_ALTIVEC" - "vmulosh %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmulosh %0,%1,%2"; + else + return "vmulesh %0,%1,%2"; +} [(set_attr "type" "veccomplex")])