From patchwork Tue Oct 15 11:23:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 283586 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BDD8A2C0146 for ; Tue, 15 Oct 2013 22:25:50 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=udA5ybGI8jNy+nv/ 64nCpJs9kU9RT9LBrzoKriqtOZK/KFS2RiEGeGuYL36OrkTCx/A1rVID2dmY6/Tp L+0bg4snwRYKl1p2p277jst5vfiHC3CuOt6em9qif7hNPx9GGYnVMKxysMQPSswB psWF1/AitE0vca4DqtVvXDRMw78= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=iNlFJ4CzWeGGOzgCGsXSSF oHOSA=; b=VMaKJPuRbCYIWajGkfwKIQeNk2rrynVo6AmBOKxUYKy/8F+WD77snY vsKdIinfAPZhycue234PR77k5dEd2dR4DDfH/0ThbU6L3CE3HoW7OeYdddgz6RLP eewAMEp77IGFutCNW+UerQsMnLaZSPIwepDqYRPJUaXaC7NMWjW4w= Received: (qmail 21600 invoked by alias); 15 Oct 2013 11:24:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 21537 invoked by uid 89); 15 Oct 2013 11:24:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 15 Oct 2013 11:24:45 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 15 Oct 2013 12:24:42 +0100 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 15 Oct 2013 12:24:40 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com, ramana.radhakrishnan@arm.com, richard.earnshaw@arm.com Subject: [AArch64] [Neon types 4/10] Add type attributes to all simd insns Date: Tue, 15 Oct 2013 12:23:40 +0100 Message-Id: <1381836226-430-5-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <1381836226-430-1-git-send-email-james.greenhalgh@arm.com> References: <1381836226-430-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113101512244201001 X-IsSubscribed: yes Hi, This patch adds the new Neon types throughout the AArch64 backend. Again, this is a churny patch, but paves the way for removing simd_type and v8type in a future patch. Tested on aarch64-none-elf with no regressions. Thanks, James --- gcc/ 2013-10-15 James Greenhalgh * config/aarch64/iterators.md (Vetype): Add SF and DF modes. (fp): New. * config/aarch64/aarch64-simd.md (neon_type): Remove. (aarch64_simd_dup): Add "type" attribute. (aarch64_dup_lane): Likewise. (aarch64_dup_lane_): Likewise. (*aarch64_simd_mov): Likewise. (aarch64_simd_mov_from_low): Likewise. (aarch64_simd_mov_from_high): Likewise. (orn3): Likewise. (bic3): Likewise. (add3): Likewise. (sub3): Likewise. (mul3): Likewise. (*aarch64_mul3_elt): Likewise. (*aarch64_mul3_elt_): Likewise. (*aarch64_mul3_elt_to_128df): Likewise. (*aarch64_mul3_elt_to_64v2df): Likewise. (neg2): Likewise. (abs2): Likewise. (abd_3): Likewise. (aba_3): Likewise. (fabd_3): Likewise. (*fabd_scalar3): Likewise. (and3): Likewise. (ior3): Likewise. (xor3): Likewise. (one_cmpl2): Likewise. (aarch64_simd_vec_set): Likewise. (aarch64_simd_lshr): Likewise. (aarch64_simd_ashr): Likewise. (aarch64_simd_imm_shl): Likewise. (aarch64_simd_reg_sshl_unsigned): Likewise. (aarch64_simd_reg_shl_signed): Likewise. (aarch64_simd_vec_setv2di): Likewise. (aarch64_simd_vec_set): Likewise. (aarch64_mla): Likewise. (*aarch64_mla_elt): Likewise. (*aarch64_mla_elt_): Likewise. (aarch64_mls): Likewise. (*aarch64_mls_elt): Likewise. (*aarch64_mls_elt_): Likewise. (3): Likewise. (move_lo_quad_): Likewise. (aarch64_simd_move_hi_quad_): Likewise. (aarch64_simd_vec_pack_trunc_): Likewise. (vec_pack_trunc_): Likewise. (aarch64_simd_vec_unpack_lo_): Likewise. (aarch64_simd_vec_unpack_hi_): Likewise. (*aarch64_mlal_lo): Likewise. (*aarch64_mlal_hi): Likewise. (*aarch64_mlsl_lo): Likewise. (*aarch64_mlsl_hi): Likewise. (*aarch64_mlal): Likewise. (*aarch64_mlsl): Likewise. (aarch64_simd_vec_mult_lo_): Likewise. (aarch64_simd_vec_mult_hi_): Likewise. (add3): Likewise. (sub3): Likewise. (mul3): Likewise. (div3): Likewise. (neg2): Likewise. (abs2): Likewise. (fma4): Likewise. (*aarch64_fma4_elt): Likewise. (*aarch64_fma4_elt_): Likewise. (*aarch64_fma4_elt_to_128df): Likewise. (*aarch64_fma4_elt_to_64v2df): Likewise. (fnma4): Likewise. (*aarch64_fnma4_elt): Likewise. (*aarch64_fnma4_elt_ (*aarch64_fnma4_elt_to_128df): Likewise. (*aarch64_fnma4_elt_to_64v2df): Likewise. (2): Likewise. (l2): Likewise. (2): Likewise. (vec_unpacks_lo_v4sf): Likewise. (aarch64_float_extend_lo_v2df): Likewise. (vec_unpacks_hi_v4sf): Likewise. (aarch64_float_truncate_lo_v2sf): Likewise. (aarch64_float_truncate_hi_v4sf): Likewise. (aarch64_vmls): Likewise. (3): Likewise. (3): Likewise. (reduc_plus_): Likewise. (reduc_plus_v2di): Likewise. (reduc_plus_v2si): Likewise. (reduc_plus_): Likewise. (aarch64_addpv4sf): Likewise. (clz2): Likewise. (reduc__): Likewise. (reduc__v2di): Likewise. (reduc__v2si): Likewise. (reduc__): Likewise. (reduc__v4sf): Likewise. (aarch64_simd_bsl_internal): Likewise. (*aarch64_get_lane_extend): Likewise. (*aarch64_get_lane_zero_extendsi): Likewise. (aarch64_get_lane): Likewise. (*aarch64_combinez): Likewise. (aarch64_combine): Likewise. (aarch64_simd_combine): Likewise. (aarch64_l_hi_internal): Likewise. (aarch64_l_lo_internal): Likewise. (aarch64_l): Likewise. (aarch64_w): Likewise. (aarch64_w2_internal): Likewise. (aarch64_h): Likewise. (aarch64_hn): Likewise. (aarch64_hn2): Likewise. (aarch64_pmul): Likewise. (aarch64_): Likewise. (aarch64_qadd): Likewise. (aarch64_sqmovun): Likewise. (aarch64_qmovn): Likewise. (aarch64_s): Likewise. (aarch64_sqdmulh): Likewise. (aarch64_sqdmulh_lane): Likewise. (aarch64_sqdmulh_laneq): Likewise. (aarch64_sqdmulh_lane): Likewise. (aarch64_sqdmll): Likewise. (aarch64_sqdmll_lane_internal): Likewise. (aarch64_sqdmll_lane_internal): Likewise. (aarch64_sqdmll_n): Likewise. (aarch64_sqdmll2_internal): Likewise. (aarch64_sqdmll2_lane_internal): Likewise. (aarch64_sqdmll2_n_internal): Likewise. (aarch64_sqdmull): Likewise. (aarch64_sqdmull_lane_internal): Likewise. (aarch64_sqdmull_n): Likewise. (aarch64_sqdmull2_internal): Likewise. (aarch64_sqdmull2_lane_internal): Likewise. (aarch64_sqdmull2_n_internal): Likewise. (aarch64_shl): Likewise. (aarch64_qshl (aarch64_shll_n): Likewise. (aarch64_shll2_n): Likewise. (aarch64_shr_n): Likewise. (aarch64_sra_n): Likewise. (aarch64_si_n): Likewise. (aarch64_qshl_n): Likewise. (aarch64_qshrn_n): Likewise. (aarch64_cm): Likewise. (aarch64_cmdi): Likewise. (aarch64_cm): Likewise. (aarch64_cmdi): Likewise. (aarch64_cmtst): Likewise. (aarch64_cmtstdi): Likewise. (aarch64_cm): Likewise. (*aarch64_fac): Likewise. (aarch64_addp): Likewise. (aarch64_addpdi): Likewise. (sqrt2): Likewise. (vec_load_lanesoi): Likewise. (vec_store_lanesoi): Likewise. (vec_load_lanesci): Likewise. (vec_store_lanesci): Likewise. (vec_load_lanesxi): Likewise. (vec_store_lanesxi): Likewise. (*aarch64_mov): Likewise. (aarch64_ld2_dreg): Likewise. (aarch64_ld2_dreg): Likewise. (aarch64_ld3_dreg): Likewise. (aarch64_ld3_dreg): Likewise. (aarch64_ld4_dreg): Likewise. (aarch64_ld4_dreg): Likewise. (aarch64_tbl1): Likewise. (aarch64_tbl2v16qi): Likewise. (aarch64_combinev16qi): Likewise. (aarch64_): Likewise. (aarch64_st2_dreg): Likewise. (aarch64_st2_dreg): Likewise. (aarch64_st3_dreg): Likewise. (aarch64_st3_dreg): Likewise. (aarch64_st4_dreg): Likewise. (aarch64_st4_dreg): Likewise. (*aarch64_simd_ld1r): Likewise. (aarch64_frecpe): Likewise. (aarch64_frecp): Likewise. (aarch64_frecps): Likewise. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index a0259b85abe37bc09584d1c9187cb6ae7d219859..a747ee8d7bade8738fabbee071ede5d1898f369e 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -238,80 +238,6 @@ (define_attr "simd_type" none" (const_string "none")) - -; The "neon_type" attribute is used by the AArch32 backend. Below is a mapping -; from "simd_type" to "neon_type". - -(define_attr "neon_type" - "neon_int_1,neon_int_2,neon_int_3,neon_int_4,neon_int_5,neon_vqneg_vqabs, - neon_vmov,neon_vaba,neon_vsma,neon_vaba_qqq, - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,neon_mul_qqq_8_16_32_ddd_32, - neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar, - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,neon_mla_qqq_8_16, - neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long, - neon_mla_qqq_32_qqd_32_scalar,neon_mul_ddd_16_scalar_32_16_long_scalar, - neon_mul_qqd_32_scalar,neon_mla_ddd_16_scalar_qdd_32_16_long_scalar, - neon_shift_1,neon_shift_2,neon_shift_3,neon_vshl_ddd, - neon_vqshl_vrshl_vqrshl_qqq,neon_vsra_vrsra,neon_fp_vadd_ddd_vabs_dd, - neon_fp_vadd_qqq_vabs_qq,neon_fp_vsum,neon_fp_vmul_ddd,neon_fp_vmul_qqd, - neon_fp_vmla_ddd,neon_fp_vmla_qqq,neon_fp_vmla_ddd_scalar, - neon_fp_vmla_qqq_scalar,neon_fp_vrecps_vrsqrts_ddd, - neon_fp_vrecps_vrsqrts_qqq,neon_bp_simple,neon_bp_2cycle,neon_bp_3cycle, - neon_ldr,neon_str,neon_vld1_1_2_regs,neon_vld1_3_4_regs, - neon_vld2_2_regs_vld1_vld2_all_lanes,neon_vld2_4_regs,neon_vld3_vld4, - neon_vst1_1_2_regs_vst2_2_regs,neon_vst1_3_4_regs, - neon_vst2_4_regs_vst3_vst4,neon_vst3_vst4,neon_vld1_vld2_lane, - neon_vld3_vld4_lane,neon_vst1_vst2_lane,neon_vst3_vst4_lane, - neon_vld3_vld4_all_lanes,neon_mcr,neon_mcr_2_mcrr,neon_mrc,neon_mrrc, - neon_ldm_2,neon_stm_2,none,unknown" - (cond [ - (eq_attr "simd_type" "simd_dup") (const_string "neon_bp_simple") - (eq_attr "simd_type" "simd_movgp") (const_string "neon_bp_simple") - (eq_attr "simd_type" "simd_add,simd_logic,simd_logic_imm") (const_string "neon_int_1") - (eq_attr "simd_type" "simd_negabs,simd_addlv") (const_string "neon_int_3") - (eq_attr "simd_type" "simd_addn,simd_addn2,simd_addl,simd_sat_add,simd_sat_negabs") (const_string "neon_int_4") - (eq_attr "simd_type" "simd_move") (const_string "neon_vmov") - (eq_attr "simd_type" "simd_ins") (const_string "neon_mcr") - (and (eq_attr "simd_type" "simd_mul,simd_sat_mul") (eq_attr "simd_mode" "V8QI,V4HI")) (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long") - (and (eq_attr "simd_type" "simd_mul,simd_sat_mul") (eq_attr "simd_mode" "V2SI,V8QI,V16QI,V2SI")) (const_string "neon_mul_qqq_8_16_32_ddd_32") - (and (eq_attr "simd_type" "simd_mull,simd_sat_mull") (eq_attr "simd_mode" "V8QI,V16QI,V4HI,V8HI")) (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long") - (and (eq_attr "simd_type" "simd_mull,simd_sat_mull") (eq_attr "simd_mode" "V2SI,V4SI,V2DI")) (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar") - (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V8QI,V4HI")) (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long") - (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V2SI")) (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long") - (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V16QI,V8HI")) (const_string "neon_mla_qqq_8_16") - (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V4SI")) (const_string "neon_mla_qqq_32_qqd_32_scalar") - (and (eq_attr "simd_type" "simd_mlal") (eq_attr "simd_mode" "V8QI,V16QI,V4HI,V8HI")) (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long") - (and (eq_attr "simd_type" "simd_mlal") (eq_attr "simd_mode" "V2SI,V4SI,V2DI")) (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long") - (and (eq_attr "simd_type" "simd_fmla") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmla_ddd") - (and (eq_attr "simd_type" "simd_fmla") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmla_qqq") - (and (eq_attr "simd_type" "simd_fmla_elt") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmla_ddd_scalar") - (and (eq_attr "simd_type" "simd_fmla_elt") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmla_qqq_scalar") - (and (eq_attr "simd_type" "simd_fmul,simd_fmul_elt,simd_fdiv,simd_fsqrt") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmul_ddd") - (and (eq_attr "simd_type" "simd_fmul,simd_fmul_elt,simd_fdiv,simd_fsqrt") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmul_qqd") - (and (eq_attr "simd_type" "simd_fadd") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vadd_ddd_vabs_dd") - (and (eq_attr "simd_type" "simd_fadd") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vadd_qqq_vabs_qq") - (and (eq_attr "simd_type" "simd_fnegabs,simd_fminmax,simd_fminmaxv") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vadd_ddd_vabs_dd") - (and (eq_attr "simd_type" "simd_fnegabs,simd_fminmax,simd_fminmaxv") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vadd_qqq_vabs_qq") - (and (eq_attr "simd_type" "simd_shift,simd_shift_acc") (eq_attr "simd_mode" "V8QI,V4HI,V2SI")) (const_string "neon_vshl_ddd") - (and (eq_attr "simd_type" "simd_shift,simd_shift_acc") (eq_attr "simd_mode" "V16QI,V8HI,V4SI,V2DI")) (const_string "neon_shift_3") - (eq_attr "simd_type" "simd_minmax,simd_minmaxv") (const_string "neon_int_5") - (eq_attr "simd_type" "simd_shiftn_imm,simd_shiftn2_imm,simd_shiftl_imm,") (const_string "neon_shift_1") - (eq_attr "simd_type" "simd_load1,simd_load2") (const_string "neon_vld1_1_2_regs") - (eq_attr "simd_type" "simd_load3,simd_load3") (const_string "neon_vld1_3_4_regs") - (eq_attr "simd_type" "simd_load1r,simd_load2r,simd_load3r,simd_load4r") (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes") - (eq_attr "simd_type" "simd_load1s,simd_load2s") (const_string "neon_vld1_vld2_lane") - (eq_attr "simd_type" "simd_load3s,simd_load4s") (const_string "neon_vld3_vld4_lane") - (eq_attr "simd_type" "simd_store1,simd_store2") (const_string "neon_vst1_1_2_regs_vst2_2_regs") - (eq_attr "simd_type" "simd_store3,simd_store4") (const_string "neon_vst1_3_4_regs") - (eq_attr "simd_type" "simd_store1s,simd_store2s") (const_string "neon_vst1_vst2_lane") - (eq_attr "simd_type" "simd_store3s,simd_store4s") (const_string "neon_vst3_vst4_lane") - (and (eq_attr "simd_type" "simd_frecpe,simd_frecps") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vrecps_vrsqrts_ddd") - (and (eq_attr "simd_type" "simd_frecpe,simd_frecps") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vrecps_vrsqrts_qqq") - (eq_attr "simd_type" "none") (const_string "none") - ] - (const_string "unknown"))) - - (define_expand "mov" [(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "") (match_operand:VALL 1 "aarch64_simd_general_operand" ""))] @@ -343,6 +269,7 @@ (define_insn "aarch64_simd_dup" dup\\t%0., %1 dup\\t%0., %1.[0]" [(set_attr "simd_type" "simd_dupgp, simd_dup") + (set_attr "type" "neon_from_gp, neon_dup") (set_attr "simd_mode" "")] ) @@ -352,6 +279,7 @@ (define_insn "aarch64_simd_dup" "TARGET_SIMD" "dup\\t%0., %1.[0]" [(set_attr "simd_type" "simd_dup") + (set_attr "type" "neon_dup") (set_attr "simd_mode" "")] ) @@ -365,6 +293,7 @@ (define_insn "aarch64_dup_lane" "TARGET_SIMD" "dup\\t%0., %1.[%2]" [(set_attr "simd_type" "simd_dup") + (set_attr "type" "neon_dup") (set_attr "simd_mode" "")] ) @@ -378,6 +307,7 @@ (define_insn "aarch64_dup_lane_, %1.[%2]" [(set_attr "simd_type" "simd_dup") + (set_attr "type" "neon_dup") (set_attr "simd_mode" "")] ) @@ -405,6 +335,9 @@ (define_insn "*aarch64_simd_mov" } } [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") + (set_attr "type" "neon_load1_1reg, neon_store1_1reg,\ + neon_logic, neon_to_gp, neon_from_gp,\ + mov_reg, neon_move") (set_attr "simd_mode" "")] ) @@ -436,6 +369,9 @@ (define_insn "*aarch64_simd_mov" } } [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") + (set_attr "type" "neon_load1_1reg, neon_store1_1reg,\ + neon_logic, multiple, multiple, multiple,\ + neon_move") (set_attr "simd_mode" "") (set_attr "length" "4,4,4,8,8,8,4")] ) @@ -516,6 +452,7 @@ (define_insn "aarch64_simd_mov_from_") (set_attr "simd_mode" "") (set_attr "length" "4") ]) @@ -528,6 +465,7 @@ (define_insn "aarch64_simd_mov_from_") (set_attr "simd_mode" "") (set_attr "length" "4") ]) @@ -539,6 +477,7 @@ (define_insn "orn3" "TARGET_SIMD" "orn\t%0., %2., %1." [(set_attr "simd_type" "simd_logic") + (set_attr "type" "neon_logic") (set_attr "simd_mode" "")] ) @@ -549,6 +488,7 @@ (define_insn "bic3" "TARGET_SIMD" "bic\t%0., %2., %1." [(set_attr "simd_type" "simd_logic") + (set_attr "type" "neon_logic") (set_attr "simd_mode" "")] ) @@ -559,6 +499,7 @@ (define_insn "add3" "TARGET_SIMD" "add\t%0., %1., %2." [(set_attr "simd_type" "simd_add") + (set_attr "type" "neon_add") (set_attr "simd_mode" "")] ) @@ -569,6 +510,7 @@ (define_insn "sub3" "TARGET_SIMD" "sub\t%0., %1., %2." [(set_attr "simd_type" "simd_add") + (set_attr "type" "neon_sub") (set_attr "simd_mode" "")] ) @@ -579,6 +521,7 @@ (define_insn "mul3" "TARGET_SIMD" "mul\t%0., %1., %2." [(set_attr "simd_type" "simd_mul") + (set_attr "type" "neon_mul_") (set_attr "simd_mode" "")] ) @@ -593,6 +536,7 @@ (define_insn "*aarch64_mul3_elt" "TARGET_SIMD" "mul\\t%0., %3., %1.[%2]" [(set_attr "simd_type" "simd_mul_elt") + (set_attr "type" "neon_mul__scalar") (set_attr "simd_mode" "")] ) @@ -607,6 +551,7 @@ (define_insn "*aarch64_mul3_elt_mul\\t%0., %3., %1.[%2]" [(set_attr "simd_type" "simd_mul_elt") + (set_attr "type" "neon_mul__scalar") (set_attr "simd_mode" "")] ) @@ -619,6 +564,7 @@ (define_insn "*aarch64_mul3_elt_to_128df "TARGET_SIMD" "fmul\\t%0.2d, %1.2d, %2.d[0]" [(set_attr "simd_type" "simd_fmul_elt") + (set_attr "type" "neon_fp_mul_d_scalar_q") (set_attr "simd_mode" "V2DF")] ) @@ -632,6 +578,7 @@ (define_insn "*aarch64_mul3_elt_to_64v2d "TARGET_SIMD" "fmul\\t%0.2d, %3.2d, %1.d[%2]" [(set_attr "simd_type" "simd_fmul_elt") + (set_attr "type" "neon_fp_mul_d_scalar_q") (set_attr "simd_mode" "V2DF")] ) @@ -641,6 +588,7 @@ (define_insn "neg2" "TARGET_SIMD" "neg\t%0., %1." [(set_attr "simd_type" "simd_negabs") + (set_attr "type" "neon_neg") (set_attr "simd_mode" "")] ) @@ -650,6 +598,7 @@ (define_insn "abs2" "TARGET_SIMD" "abs\t%0., %1." [(set_attr "simd_type" "simd_negabs") + (set_attr "type" "neon_abs") (set_attr "simd_mode" "")] ) @@ -661,6 +610,7 @@ (define_insn "abd_3" "TARGET_SIMD" "sabd\t%0., %1., %2." [(set_attr "simd_type" "simd_abd") + (set_attr "type" "neon_abd") (set_attr "simd_mode" "")] ) @@ -673,6 +623,7 @@ (define_insn "aba_3" "TARGET_SIMD" "saba\t%0., %1., %2." [(set_attr "simd_type" "simd_abd") + (set_attr "type" "neon_arith_acc") (set_attr "simd_mode" "")] ) @@ -684,6 +635,7 @@ (define_insn "fabd_3" "TARGET_SIMD" "fabd\t%0., %1., %2." [(set_attr "simd_type" "simd_fabd") + (set_attr "type" "neon_fp_abd_") (set_attr "simd_mode" "")] ) @@ -695,6 +647,7 @@ (define_insn "*fabd_scalar3" "TARGET_SIMD" "fabd\t%0, %1, %2" [(set_attr "simd_type" "simd_fabd") + (set_attr "type" "neon_fp_abd_") (set_attr "mode" "")] ) @@ -705,6 +658,7 @@ (define_insn "and3" "TARGET_SIMD" "and\t%0., %1., %2." [(set_attr "simd_type" "simd_logic") + (set_attr "type" "neon_logic") (set_attr "simd_mode" "")] ) @@ -715,6 +669,7 @@ (define_insn "ior3" "TARGET_SIMD" "orr\t%0., %1., %2." [(set_attr "simd_type" "simd_logic") + (set_attr "type" "neon_logic") (set_attr "simd_mode" "")] ) @@ -725,6 +680,7 @@ (define_insn "xor3" "TARGET_SIMD" "eor\t%0., %1., %2." [(set_attr "simd_type" "simd_logic") + (set_attr "type" "neon_logic") (set_attr "simd_mode" "")] ) @@ -734,6 +690,7 @@ (define_insn "one_cmpl2" "TARGET_SIMD" "not\t%0., %1." [(set_attr "simd_type" "simd_logic") + (set_attr "type" "neon_logic") (set_attr "simd_mode" "")] ) @@ -747,6 +704,7 @@ (define_insn "aarch64_simd_vec_set "TARGET_SIMD" "ins\t%0.[%p2], %w1"; [(set_attr "simd_type" "simd_insgp") + (set_attr "type" "neon_from_gp") (set_attr "simd_mode" "")] ) @@ -757,6 +715,7 @@ (define_insn "aarch64_simd_lshr" "TARGET_SIMD" "ushr\t%0., %1., %2" [(set_attr "simd_type" "simd_shift_imm") + (set_attr "type" "neon_shift_imm") (set_attr "simd_mode" "")] ) @@ -767,6 +726,7 @@ (define_insn "aarch64_simd_ashr" "TARGET_SIMD" "sshr\t%0., %1., %2" [(set_attr "simd_type" "simd_shift_imm") + (set_attr "type" "neon_shift_imm") (set_attr "simd_mode" "")] ) @@ -777,6 +737,7 @@ (define_insn "aarch64_simd_imm_shl "TARGET_SIMD" "shl\t%0., %1., %2" [(set_attr "simd_type" "simd_shift_imm") + (set_attr "type" "neon_shift_imm") (set_attr "simd_mode" "")] ) @@ -787,6 +748,7 @@ (define_insn "aarch64_simd_reg_sshl, %1., %2." [(set_attr "simd_type" "simd_shift") + (set_attr "type" "neon_shift_reg") (set_attr "simd_mode" "")] ) @@ -798,6 +760,7 @@ (define_insn "aarch64_simd_reg_shl "TARGET_SIMD" "ushl\t%0., %1., %2." [(set_attr "simd_type" "simd_shift") + (set_attr "type" "neon_shift_reg") (set_attr "simd_mode" "")] ) @@ -809,6 +772,7 @@ (define_insn "aarch64_simd_reg_shl "TARGET_SIMD" "sshl\t%0., %1., %2." [(set_attr "simd_type" "simd_shift") + (set_attr "type" "neon_shift_reg") (set_attr "simd_mode" "")] ) @@ -1016,6 +980,7 @@ (define_insn "aarch64_simd_vec_setv2di" "TARGET_SIMD" "ins\t%0.d[%p2], %1"; [(set_attr "simd_type" "simd_insgp") + (set_attr "type" "neon_from_gp") (set_attr "simd_mode" "V2DI")] ) @@ -1042,6 +1007,7 @@ (define_insn "aarch64_simd_vec_set "TARGET_SIMD" "ins\t%0.[%p2], %1.[0]"; [(set_attr "simd_type" "simd_ins") + (set_attr "type" "neon_ins") (set_attr "simd_mode" "")] ) @@ -1067,6 +1033,7 @@ (define_insn "aarch64_mla" "TARGET_SIMD" "mla\t%0., %2., %3." [(set_attr "simd_type" "simd_mla") + (set_attr "type" "neon_mla_") (set_attr "simd_mode" "")] ) @@ -1083,6 +1050,7 @@ (define_insn "*aarch64_mla_elt" "TARGET_SIMD" "mla\t%0., %3., %1.[%2]" [(set_attr "simd_type" "simd_mla") + (set_attr "type" "neon_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1099,6 +1067,7 @@ (define_insn "*aarch64_mla_elt_, %3., %1.[%2]" [(set_attr "simd_type" "simd_mla") + (set_attr "type" "neon_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1110,6 +1079,7 @@ (define_insn "aarch64_mls" "TARGET_SIMD" "mls\t%0., %2., %3." [(set_attr "simd_type" "simd_mla") + (set_attr "type" "neon_mla_") (set_attr "simd_mode" "")] ) @@ -1126,6 +1096,7 @@ (define_insn "*aarch64_mls_elt" "TARGET_SIMD" "mls\t%0., %3., %1.[%2]" [(set_attr "simd_type" "simd_mla") + (set_attr "type" "neon_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1142,6 +1113,7 @@ (define_insn "*aarch64_mls_elt_, %3., %1.[%2]" [(set_attr "simd_type" "simd_mla") + (set_attr "type" "neon_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1153,6 +1125,7 @@ (define_insn "3" "TARGET_SIMD" "\t%0., %1., %2." [(set_attr "simd_type" "simd_minmax") + (set_attr "type" "neon_minmax") (set_attr "simd_mode" "")] ) @@ -1169,7 +1142,7 @@ (define_insn "move_lo_quad_" fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "v8type" "*,fmov,*") - (set_attr "type" "*,fmov,*") + (set_attr "type" "neon_dup,fmov,neon_dup") (set_attr "simd_type" "simd_dup,*,simd_dup") (set_attr "simd_mode" "") (set_attr "simd" "yes,*,yes") @@ -1191,6 +1164,7 @@ (define_insn "aarch64_simd_move_hi_quad_ ins\\t%0.d[1], %1.d[0] ins\\t%0.d[1], %1" [(set_attr "simd_type" "simd_ins,simd_ins") + (set_attr "type" "neon_ins") (set_attr "simd_mode" "") (set_attr "length" "4")] ) @@ -1215,6 +1189,7 @@ (define_insn "aarch64_simd_vec_pack_trun "TARGET_SIMD" "xtn\\t%0., %1." [(set_attr "simd_type" "simd_shiftn_imm") + (set_attr "type" "neon_shift_imm_narrow_q") (set_attr "simd_mode" "")] ) @@ -1242,6 +1217,7 @@ (define_insn "vec_pack_trunc_" "TARGET_SIMD" "xtn\\t%0., %1.\;xtn2\\t%0., %2." [(set_attr "simd_type" "simd_shiftn2_imm") + (set_attr "type" "multiple") (set_attr "simd_mode" "") (set_attr "length" "8")] ) @@ -1257,6 +1233,7 @@ (define_insn "aarch64_simd_vec_unpackshll %0., %1., 0" [(set_attr "simd_type" "simd_shiftl_imm") + (set_attr "type" "neon_shift_imm_long") (set_attr "simd_mode" "")] ) @@ -1269,6 +1246,7 @@ (define_insn "aarch64_simd_vec_unpackshll2 %0., %1., 0" [(set_attr "simd_type" "simd_shiftl_imm") + (set_attr "type" "neon_shift_imm_long") (set_attr "simd_mode" "")] ) @@ -1312,6 +1290,7 @@ (define_insn "*aarch64_mlal_lo "TARGET_SIMD" "mlal\t%0., %2., %4." [(set_attr "simd_type" "simd_mlal") + (set_attr "type" "neon_mla__long") (set_attr "simd_mode" "")] ) @@ -1329,6 +1308,7 @@ (define_insn "*aarch64_mlal_hi "TARGET_SIMD" "mlal2\t%0., %2., %4." [(set_attr "simd_type" "simd_mlal") + (set_attr "type" "neon_mla__long") (set_attr "simd_mode" "")] ) @@ -1346,6 +1326,7 @@ (define_insn "*aarch64_mlsl_lo "TARGET_SIMD" "mlsl\t%0., %2., %4." [(set_attr "simd_type" "simd_mlal") + (set_attr "type" "neon_mla__long") (set_attr "simd_mode" "")] ) @@ -1363,6 +1344,7 @@ (define_insn "*aarch64_mlsl_hi "TARGET_SIMD" "mlsl2\t%0., %2., %4." [(set_attr "simd_type" "simd_mlal") + (set_attr "type" "neon_mla__long") (set_attr "simd_mode" "")] ) @@ -1378,6 +1360,7 @@ (define_insn "*aarch64_mlal" "TARGET_SIMD" "mlal\t%0., %1., %2." [(set_attr "simd_type" "simd_mlal") + (set_attr "type" "neon_mla__long") (set_attr "simd_mode" "")] ) @@ -1393,6 +1376,7 @@ (define_insn "*aarch64_mlsl" "TARGET_SIMD" "mlsl\t%0., %2., %3." [(set_attr "simd_type" "simd_mlal") + (set_attr "type" "neon_mla__long") (set_attr "simd_mode" "")] ) @@ -1407,6 +1391,7 @@ (define_insn "aarch64_simd_vec_mult_ "TARGET_SIMD" "mull\\t%0., %1., %2." [(set_attr "simd_type" "simd_mull") + (set_attr "type" "neon_mul__long") (set_attr "simd_mode" "")] ) @@ -1435,6 +1420,7 @@ (define_insn "aarch64_simd_vec_mult_ "TARGET_SIMD" "mull2\\t%0., %1., %2." [(set_attr "simd_type" "simd_mull") + (set_attr "type" "neon_mul__long") (set_attr "simd_mode" "")] ) @@ -1485,6 +1471,7 @@ (define_insn "add3" "TARGET_SIMD" "fadd\\t%0., %1., %2." [(set_attr "simd_type" "simd_fadd") + (set_attr "type" "neon_fp_addsub_") (set_attr "simd_mode" "")] ) @@ -1495,6 +1482,7 @@ (define_insn "sub3" "TARGET_SIMD" "fsub\\t%0., %1., %2." [(set_attr "simd_type" "simd_fadd") + (set_attr "type" "neon_fp_addsub_") (set_attr "simd_mode" "")] ) @@ -1505,6 +1493,7 @@ (define_insn "mul3" "TARGET_SIMD" "fmul\\t%0., %1., %2." [(set_attr "simd_type" "simd_fmul") + (set_attr "type" "neon_fp_mul_") (set_attr "simd_mode" "")] ) @@ -1515,6 +1504,7 @@ (define_insn "div3" "TARGET_SIMD" "fdiv\\t%0., %1., %2." [(set_attr "simd_type" "simd_fdiv") + (set_attr "type" "neon_fp_div_") (set_attr "simd_mode" "")] ) @@ -1524,6 +1514,7 @@ (define_insn "neg2" "TARGET_SIMD" "fneg\\t%0., %1." [(set_attr "simd_type" "simd_fnegabs") + (set_attr "type" "neon_fp_neg_") (set_attr "simd_mode" "")] ) @@ -1533,6 +1524,7 @@ (define_insn "abs2" "TARGET_SIMD" "fabs\\t%0., %1." [(set_attr "simd_type" "simd_fnegabs") + (set_attr "type" "neon_fp_abs_") (set_attr "simd_mode" "")] ) @@ -1544,6 +1536,7 @@ (define_insn "fma4" "TARGET_SIMD" "fmla\\t%0., %1., %2." [(set_attr "simd_type" "simd_fmla") + (set_attr "type" "neon_fp_mla_") (set_attr "simd_mode" "")] ) @@ -1559,6 +1552,7 @@ (define_insn "*aarch64_fma4_elt" "TARGET_SIMD" "fmla\\t%0., %3., %1.[%2]" [(set_attr "simd_type" "simd_fmla_elt") + (set_attr "type" "neon_fp_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1574,6 +1568,7 @@ (define_insn "*aarch64_fma4_elt_, %3., %1.[%2]" [(set_attr "simd_type" "simd_fmla_elt") + (set_attr "type" "neon_fp_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1587,6 +1582,7 @@ (define_insn "*aarch64_fma4_elt_to_128df "TARGET_SIMD" "fmla\\t%0.2d, %2.2d, %1.2d[0]" [(set_attr "simd_type" "simd_fmla_elt") + (set_attr "type" "neon_fp_mla_d_scalar_q") (set_attr "simd_mode" "V2DF")] ) @@ -1601,6 +1597,7 @@ (define_insn "*aarch64_fma4_elt_to_64v2d "TARGET_SIMD" "fmla\\t%0.2d, %3.2d, %1.2d[%2]" [(set_attr "simd_type" "simd_fmla_elt") + (set_attr "type" "neon_fp_mla_d_scalar_q") (set_attr "simd_mode" "V2DF")] ) @@ -1614,6 +1611,7 @@ (define_insn "fnma4" "TARGET_SIMD" "fmls\\t%0., %1., %2." [(set_attr "simd_type" "simd_fmla") + (set_attr "type" "neon_fp_mla_") (set_attr "simd_mode" "")] ) @@ -1630,6 +1628,7 @@ (define_insn "*aarch64_fnma4_elt" "TARGET_SIMD" "fmls\\t%0., %3., %1.[%2]" [(set_attr "simd_type" "simd_fmla_elt") + (set_attr "type" "neon_fp_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1646,6 +1645,7 @@ (define_insn "*aarch64_fnma4_elt_, %3., %1.[%2]" [(set_attr "simd_type" "simd_fmla_elt") + (set_attr "type" "neon_fp_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1660,6 +1660,7 @@ (define_insn "*aarch64_fnma4_elt_to_128d "TARGET_SIMD" "fmls\\t%0.2d, %2.2d, %1.2d[0]" [(set_attr "simd_type" "simd_fmla_elt") + (set_attr "type" "neon_fp_mla_d_scalar_q") (set_attr "simd_mode" "V2DF")] ) @@ -1675,6 +1676,7 @@ (define_insn "*aarch64_fnma4_elt_to_64v2 "TARGET_SIMD" "fmls\\t%0.2d, %3.2d, %1.2d[%2]" [(set_attr "simd_type" "simd_fmla_elt") + (set_attr "type" "neon_fp_mla_d_scalar_q") (set_attr "simd_mode" "V2DF")] ) @@ -1687,6 +1689,7 @@ (define_insn "2" "TARGET_SIMD" "frint\\t%0., %1." [(set_attr "simd_type" "simd_frint") + (set_attr "type" "neon_fp_round_") (set_attr "simd_mode" "")] ) @@ -1700,6 +1703,7 @@ (define_insn "l< "TARGET_SIMD" "fcvt\\t%0., %1." [(set_attr "simd_type" "simd_fcvti") + (set_attr "type" "neon_fp_to_int_") (set_attr "simd_mode" "")] ) @@ -1733,6 +1737,7 @@ (define_insn "cvtf\\t%0., %1." [(set_attr "simd_type" "simd_icvtf") + (set_attr "type" "neon_int_to_fp_") (set_attr "simd_mode" "")] ) @@ -1752,6 +1757,7 @@ (define_insn "vec_unpacks_lo_v4sf" "TARGET_SIMD" "fcvtl\\t%0.2d, %1.2s" [(set_attr "simd_type" "simd_fcvtl") + (set_attr "type" "neon_fp_cvt_widen_s") (set_attr "simd_mode" "V2DF")] ) @@ -1762,6 +1768,7 @@ (define_insn "aarch64_float_extend_lo_v2 "TARGET_SIMD" "fcvtl\\t%0.2d, %1.2s" [(set_attr "simd_type" "simd_fcvtl") + (set_attr "type" "neon_fp_cvt_widen_s") (set_attr "simd_mode" "V2DF")] ) @@ -1775,6 +1782,7 @@ (define_insn "vec_unpacks_hi_v4sf" "TARGET_SIMD" "fcvtl2\\t%0.2d, %1.4s" [(set_attr "simd_type" "simd_fcvtl") + (set_attr "type" "neon_fp_cvt_widen_s") (set_attr "simd_mode" "V2DF")] ) @@ -1787,6 +1795,7 @@ (define_insn "aarch64_float_truncate_lo_ "TARGET_SIMD" "fcvtn\\t%0.2s, %1.2d" [(set_attr "simd_type" "simd_fcvtl") + (set_attr "type" "neon_fp_cvt_narrow_d_q") (set_attr "simd_mode" "V2SF")] ) @@ -1799,6 +1808,7 @@ (define_insn "aarch64_float_truncate_hi_ "TARGET_SIMD" "fcvtn2\\t%0.4s, %2.2d" [(set_attr "simd_type" "simd_fcvtl") + (set_attr "type" "neon_fp_cvt_narrow_d_q") (set_attr "simd_mode" "V4SF")] ) @@ -1846,6 +1856,7 @@ (define_insn "aarch64_vmls" "TARGET_SIMD" "fmls\\t%0., %2., %3." [(set_attr "simd_type" "simd_fmla") + (set_attr "type" "neon_fp_mla__scalar") (set_attr "simd_mode" "")] ) @@ -1870,6 +1881,7 @@ (define_insn "3" "TARGET_SIMD" "fnm\\t%0., %1., %2." [(set_attr "simd_type" "simd_fminmax") + (set_attr "type" "neon_fp_minmax_") (set_attr "simd_mode" "")] ) @@ -1881,6 +1893,7 @@ (define_insn "3" "TARGET_SIMD" "\\t%0., %1., %2." [(set_attr "simd_type" "simd_fminmax") + (set_attr "type" "neon_fp_minmax_") (set_attr "simd_mode" "")] ) @@ -1893,6 +1906,7 @@ (define_insn "reduc_plus_" "TARGET_SIMD" "addv\\t%0, %1." [(set_attr "simd_type" "simd_addv") + (set_attr "type" "neon_reduc_add") (set_attr "simd_mode" "")] ) @@ -1903,6 +1917,7 @@ (define_insn "reduc_plus_v2di" "TARGET_SIMD" "addp\\t%d0, %1.2d" [(set_attr "simd_type" "simd_addv") + (set_attr "type" "neon_reduc_add_q") (set_attr "simd_mode" "V2DI")] ) @@ -1913,6 +1928,7 @@ (define_insn "reduc_plus_v2si" "TARGET_SIMD" "addp\\t%0.2s, %1.2s, %1.2s" [(set_attr "simd_type" "simd_addv") + (set_attr "type" "neon_reduc_add") (set_attr "simd_mode" "V2SI")] ) @@ -1923,6 +1939,7 @@ (define_insn "reduc_plus_" "TARGET_SIMD" "faddp\\t%0, %1." [(set_attr "simd_type" "simd_fadd") + (set_attr "type" "neon_fp_reduc_add_") (set_attr "simd_mode" "")] ) @@ -1933,6 +1950,7 @@ (define_insn "aarch64_addpv4sf" "TARGET_SIMD" "faddp\\t%0.4s, %1.4s, %1.4s" [(set_attr "simd_type" "simd_fadd") + (set_attr "type" "neon_fp_reduc_add_s_q") (set_attr "simd_mode" "V4SF")] ) @@ -1954,6 +1972,7 @@ (define_insn "clz2" "TARGET_SIMD" "clz\\t%0., %1." [(set_attr "simd_type" "simd_cls") + (set_attr "type" "neon_cls") (set_attr "simd_mode" "")] ) @@ -1966,6 +1985,7 @@ (define_insn "reduc__" "TARGET_SIMD" "v\\t%0, %1." [(set_attr "simd_type" "simd_minmaxv") + (set_attr "type" "neon_reduc_minmax") (set_attr "simd_mode" "")] ) @@ -1976,6 +1996,7 @@ (define_insn "reduc__v2di" "TARGET_SIMD" "p\\t%d0, %1.2d" [(set_attr "simd_type" "simd_minmaxv") + (set_attr "type" "neon_reduc_minmax_q") (set_attr "simd_mode" "V2DI")] ) @@ -1986,6 +2007,7 @@ (define_insn "reduc__v2si" "TARGET_SIMD" "p\\t%0.2s, %1.2s, %1.2s" [(set_attr "simd_type" "simd_minmaxv") + (set_attr "type" "neon_reduc_minmax") (set_attr "simd_mode" "V2SI")] ) @@ -1996,6 +2018,7 @@ (define_insn "reduc__" "TARGET_SIMD" "p\\t%0, %1." [(set_attr "simd_type" "simd_fminmaxv") + (set_attr "type" "neon_fp_reduc_minmax_") (set_attr "simd_mode" "")] ) @@ -2006,6 +2029,7 @@ (define_insn "reduc__v4sf" "TARGET_SIMD" "v\\t%s0, %1.4s" [(set_attr "simd_type" "simd_fminmaxv") + (set_attr "type" "neon_fp_reduc_minmax_s_q") (set_attr "simd_mode" "V4SF")] ) @@ -2041,6 +2065,8 @@ (define_insn "aarch64_simd_bsl_int bsl\\t%0., %2., %3. bit\\t%0., %2., %1. bif\\t%0., %3., %1." + [(set_attr "simd_mode" "") + (set_attr "type" "neon_bsl")] ) (define_expand "aarch64_simd_bsl" @@ -2406,6 +2432,7 @@ (define_insn "*aarch64_get_lane_extend0, %1.[%2]" [(set_attr "simd_type" "simd_movgp") + (set_attr "type" "neon_to_gp") (set_attr "simd_mode" "")] ) @@ -2418,6 +2445,7 @@ (define_insn "*aarch64_get_lane_zero_ext "TARGET_SIMD" "umov\\t%w0, %1.[%2]" [(set_attr "simd_type" "simd_movgp") + (set_attr "type" "neon_to_gp") (set_attr "simd_mode" "")] ) @@ -2433,6 +2461,7 @@ (define_insn "aarch64_get_lane" umov\\t%0, %1.[%2] dup\\t%0, %1.[%2]" [(set_attr "simd_type" "simd_movgp, simd_dup") + (set_attr "type" "neon_to_gp, neon_dup") (set_attr "simd_mode" "")] ) @@ -2557,6 +2586,7 @@ (define_insn "*aarch64_combinez" "TARGET_SIMD" "mov\\t%0.8b, %1.8b" [(set_attr "simd_type" "simd_move") + (set_attr "type" "neon_move") (set_attr "simd_mode" "")] ) @@ -2571,7 +2601,9 @@ (define_insn_and_split "aarch64_combine< { aarch64_split_simd_combine (operands[0], operands[1], operands[2]); DONE; -}) +} +[(set_attr "type" "multiple")] +) (define_expand "aarch64_simd_combine" [(set (match_operand: 0 "register_operand" "=&w") @@ -2582,7 +2614,9 @@ (define_expand "aarch64_simd_combine (operands[0], operands[1])); emit_insn (gen_move_hi_quad_ (operands[0], operands[2])); DONE; - }) + } +[(set_attr "type" "multiple")] +) ;; l. @@ -2597,6 +2631,7 @@ (define_insn "aarch64_l2\t%0., %1., %2." [(set_attr "simd_type" "simd_addl") + (set_attr "type" "neon__long") (set_attr "simd_mode" "")] ) @@ -2611,6 +2646,7 @@ (define_insn "aarch64_l\t%0., %1., %2." [(set_attr "simd_type" "simd_addl") + (set_attr "type" "neon__long") (set_attr "simd_mode" "")] ) @@ -2672,6 +2708,7 @@ (define_insn "aarch64_l %0., %1., %2." [(set_attr "simd_type" "simd_addl") + (set_attr "type" "neon__long") (set_attr "simd_mode" "")] ) @@ -2685,6 +2722,7 @@ (define_insn "aarch64_w\\t%0., %1., %2." [(set_attr "simd_type" "simd_addl") + (set_attr "type" "neon__widen") (set_attr "simd_mode" "")] ) @@ -2698,6 +2736,7 @@ (define_insn "aarch64_w2\\t%0., %1., %2." [(set_attr "simd_type" "simd_addl") + (set_attr "type" "neon__widen") (set_attr "simd_mode" "")] ) @@ -2760,6 +2799,7 @@ (define_insn "aarch64_hh\\t%0., %1., %2." [(set_attr "simd_type" "simd_add") + (set_attr "type" "neon__halve") (set_attr "simd_mode" "")] ) @@ -2773,6 +2813,7 @@ (define_insn "aarch64_hnhn\\t%0., %1., %2." [(set_attr "simd_type" "simd_addn") + (set_attr "type" "neon__halve_narrow_q") (set_attr "simd_mode" "")] ) @@ -2785,6 +2826,7 @@ (define_insn "aarch64_hn2hn2\\t%0., %2., %3." [(set_attr "simd_type" "simd_addn2") + (set_attr "type" "neon__halve_narrow_q") (set_attr "simd_mode" "")] ) @@ -2798,6 +2840,7 @@ (define_insn "aarch64_pmul" "TARGET_SIMD" "pmul\\t%0., %1., %2." [(set_attr "simd_type" "simd_mul") + (set_attr "type" "neon_mul_") (set_attr "simd_mode" "")] ) @@ -2810,6 +2853,7 @@ (define_insn "aarch64_< "TARGET_SIMD" "\\t%0, %1, %2" [(set_attr "simd_type" "simd_add") + (set_attr "type" "neon_") (set_attr "simd_mode" "")] ) @@ -2823,6 +2867,7 @@ (define_insn "aarch64_qadd" "TARGET_SIMD" "qadd\\t%0, %2" [(set_attr "simd_type" "simd_sat_add") + (set_attr "type" "neon_qadd") (set_attr "simd_mode" "")] ) @@ -2835,6 +2880,7 @@ (define_insn "aarch64_sqmovun" "TARGET_SIMD" "sqxtun\\t%0, %1" [(set_attr "simd_type" "simd_sat_shiftn_imm") + (set_attr "type" "neon_sat_shift_imm_narrow_q") (set_attr "simd_mode" "")] ) @@ -2847,6 +2893,7 @@ (define_insn "aarch64_qmovn" "TARGET_SIMD" "qxtn\\t%0, %1" [(set_attr "simd_type" "simd_sat_shiftn_imm") + (set_attr "type" "neon_sat_shift_imm_narrow_q") (set_attr "simd_mode" "")] ) @@ -2859,6 +2906,7 @@ (define_insn "aarch64_s" "TARGET_SIMD" "s\\t%0, %1" [(set_attr "simd_type" "simd_sat_negabs") + (set_attr "type" "neon_") (set_attr "simd_mode" "")] ) @@ -2873,6 +2921,7 @@ (define_insn "aarch64_sqdmulh" "TARGET_SIMD" "sqdmulh\\t%0, %1, %2" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul_") (set_attr "simd_mode" "")] ) @@ -2891,6 +2940,7 @@ (define_insn "aarch64_sqdmulh_lanemode)); return \"sqdmulh\\t%0., %1., %2.[%3]\";" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar") (set_attr "simd_mode" "")] ) @@ -2907,6 +2957,7 @@ (define_insn "aarch64_sqdmulh_laneqmode)); return \"sqdmulh\\t%0., %1., %2.[%3]\";" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar") (set_attr "simd_mode" "")] ) @@ -2923,6 +2974,7 @@ (define_insn "aarch64_sqdmulh_lanemode)); return \"sqdmulh\\t%0, %1, %2.[%3]\";" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar") (set_attr "simd_mode" "")] ) @@ -2942,6 +2994,7 @@ (define_insn "aarch64_sqdml "TARGET_SIMD" "sqdmll\\t%0, %2, %3" [(set_attr "simd_type" "simd_sat_mlal") + (set_attr "type" "neon_sat_mla__long") (set_attr "simd_mode" "")] ) @@ -2965,6 +3018,7 @@ (define_insn "aarch64_sqdml "TARGET_SIMD" "sqdmll\\t%0, %2, %3.[%4]" [(set_attr "simd_type" "simd_sat_mlal") + (set_attr "type" "neon_sat_mla__scalar_long") (set_attr "simd_mode" "")] ) @@ -2985,6 +3039,7 @@ (define_insn "aarch64_sqdml "TARGET_SIMD" "sqdmll\\t%0, %2, %3.[%4]" [(set_attr "simd_type" "simd_sat_mlal") + (set_attr "type" "neon_sat_mla__scalar_long") (set_attr "simd_mode" "")] ) @@ -3065,6 +3120,7 @@ (define_insn "aarch64_sqdml "TARGET_SIMD" "sqdmll\\t%0, %2, %3.[0]" [(set_attr "simd_type" "simd_sat_mlal") + (set_attr "type" "neon_sat_mla__scalar_long") (set_attr "simd_mode" "")] ) @@ -3088,6 +3144,7 @@ (define_insn "aarch64_sqdml "TARGET_SIMD" "sqdmll2\\t%0, %2, %3" [(set_attr "simd_type" "simd_sat_mlal") + (set_attr "type" "neon_sat_mla__scalar_long") (set_attr "simd_mode" "")] ) @@ -3139,6 +3196,7 @@ (define_insn "aarch64_sqdml "TARGET_SIMD" "sqdmll2\\t%0, %2, %3.[%4]" [(set_attr "simd_type" "simd_sat_mlal") + (set_attr "type" "neon_sat_mla__scalar_long") (set_attr "simd_mode" "")] ) @@ -3223,6 +3281,7 @@ (define_insn "aarch64_sqdml "TARGET_SIMD" "sqdmll2\\t%0, %2, %3.[0]" [(set_attr "simd_type" "simd_sat_mlal") + (set_attr "type" "neon_sat_mla__scalar_long") (set_attr "simd_mode" "")] ) @@ -3268,6 +3327,7 @@ (define_insn "aarch64_sqdmull" "TARGET_SIMD" "sqdmull\\t%0, %1, %2" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__long") (set_attr "simd_mode" "")] ) @@ -3289,6 +3349,7 @@ (define_insn "aarch64_sqdmull_lane "TARGET_SIMD" "sqdmull\\t%0, %1, %2.[%3]" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar_long") (set_attr "simd_mode" "")] ) @@ -3307,6 +3368,7 @@ (define_insn "aarch64_sqdmull_lane "TARGET_SIMD" "sqdmull\\t%0, %1, %2.[%3]" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar_long") (set_attr "simd_mode" "")] ) @@ -3352,6 +3414,7 @@ (define_insn "aarch64_sqdmull_n" "TARGET_SIMD" "sqdmull\\t%0, %1, %2.[0]" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar_long") (set_attr "simd_mode" "")] ) @@ -3376,6 +3439,7 @@ (define_insn "aarch64_sqdmull2_int "TARGET_SIMD" "sqdmull2\\t%0, %1, %2" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar_long") (set_attr "simd_mode" "")] ) @@ -3411,6 +3475,7 @@ (define_insn "aarch64_sqdmull2_lane0, %1, %2.[%3]" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar_long") (set_attr "simd_mode" "")] ) @@ -3462,6 +3527,7 @@ (define_insn "aarch64_sqdmull2_n_i "TARGET_SIMD" "sqdmull2\\t%0, %1, %2.[0]" [(set_attr "simd_type" "simd_sat_mul") + (set_attr "type" "neon_sat_mul__scalar_long") (set_attr "simd_mode" "")] ) @@ -3488,6 +3554,7 @@ (define_insn "aarch64_shl" "TARGET_SIMD" "shl\\t%0, %1, %2"; [(set_attr "simd_type" "simd_shift") + (set_attr "type" "neon_shift_reg") (set_attr "simd_mode" "")] ) @@ -3503,6 +3570,7 @@ (define_insn "aarch64_qshl "TARGET_SIMD" "qshl\\t%0, %1, %2"; [(set_attr "simd_type" "simd_sat_shift") + (set_attr "type" "neon_sat_shift_reg") (set_attr "simd_mode" "")] ) @@ -3525,6 +3593,7 @@ (define_insn "aarch64_shll_n" return \"shll\\t%0., %1., %2\"; }" [(set_attr "simd_type" "simd_shift_imm") + (set_attr "type" "neon_shift_imm_long") (set_attr "simd_mode" "")] ) @@ -3547,6 +3616,7 @@ (define_insn "aarch64_shll2_n return \"shll2\\t%0., %1., %2\"; }" [(set_attr "simd_type" "simd_shift_imm") + (set_attr "type" "neon_shift_imm_long") (set_attr "simd_mode" "")] ) @@ -3563,6 +3633,7 @@ (define_insn "aarch64_shr_n" aarch64_simd_const_bounds (operands[2], 1, bit_width + 1); return \"shr\\t%0, %1, %2\";" [(set_attr "simd_type" "simd_shift_imm") + (set_attr "type" "neon_sat_shift_imm") (set_attr "simd_mode" "")] ) @@ -3580,6 +3651,7 @@ (define_insn "aarch64_sra_n" aarch64_simd_const_bounds (operands[3], 1, bit_width + 1); return \"sra\\t%0, %2, %3\";" [(set_attr "simd_type" "simd_shift_imm_acc") + (set_attr "type" "neon_shift_acc") (set_attr "simd_mode" "")] ) @@ -3598,6 +3670,7 @@ (define_insn "aarch64_si_n + 1); return \"si\\t%0, %2, %3\";" [(set_attr "simd_type" "simd_shift_imm") + (set_attr "type" "neon_shift_imm") (set_attr "simd_mode" "")] ) @@ -3614,6 +3687,7 @@ (define_insn "aarch64_qshl_nqshl\\t%0, %1, %2\";" [(set_attr "simd_type" "simd_sat_shift_imm") + (set_attr "type" "neon_sat_shift_imm") (set_attr "simd_mode" "")] ) @@ -3631,6 +3705,7 @@ (define_insn "aarch64_qshrn_n aarch64_simd_const_bounds (operands[2], 1, bit_width + 1); return \"qshrn\\t%0, %1, %2\";" [(set_attr "simd_type" "simd_sat_shiftn_imm") + (set_attr "type" "neon_sat_shift_imm_narrow_q") (set_attr "simd_mode" "")] ) @@ -3651,6 +3726,7 @@ (define_insn "aarch64_cm" cm\t%0, %, % cm\t%0, %1, #0" [(set_attr "simd_type" "simd_cmp") + (set_attr "type" "neon_compare, neon_compare_zero") (set_attr "simd_mode" "")] ) @@ -3681,6 +3757,7 @@ (define_insn_and_split "aarch64_cm" "TARGET_SIMD" "cm\t%0, %, %" [(set_attr "simd_type" "simd_cmp") + (set_attr "type" "neon_compare") (set_attr "simd_mode" "")] ) @@ -3725,6 +3803,7 @@ (define_insn_and_split "aarch64_cm" "TARGET_SIMD" "cmtst\t%0, %1, %2" [(set_attr "simd_type" "simd_cmp") + (set_attr "type" "neon_tst") (set_attr "simd_mode" "")] ) @@ -3772,6 +3852,7 @@ (define_insn_and_split "aarch64_cmtstdi" DONE; } [(set_attr "simd_type" "simd_cmp") + (set_attr "type" "neon_tst") (set_attr "simd_mode" "DI")] ) @@ -3789,6 +3870,7 @@ (define_insn "aarch64_cm" fcm\t%0, %, % fcm\t%0, %1, 0" [(set_attr "simd_type" "simd_fcmp") + (set_attr "type" "neon_fp_compare_") (set_attr "simd_mode" "")] ) @@ -3806,6 +3888,7 @@ (define_insn "*aarch64_fac" "TARGET_SIMD" "fac\t%0, %, %" [(set_attr "simd_type" "simd_fcmp") + (set_attr "type" "neon_fp_compare_") (set_attr "simd_mode" "")] ) @@ -3820,6 +3903,7 @@ (define_insn "aarch64_addp" "TARGET_SIMD" "addp\t%0, %1, %2" [(set_attr "simd_type" "simd_add") + (set_attr "type" "neon_reduc_add") (set_attr "simd_mode" "")] ) @@ -3831,6 +3915,7 @@ (define_insn "aarch64_addpdi" "TARGET_SIMD" "addp\t%d0, %1.2d" [(set_attr "simd_type" "simd_add") + (set_attr "type" "neon_reduc_add") (set_attr "simd_mode" "DI")] ) @@ -3842,6 +3927,7 @@ (define_insn "sqrt2" "TARGET_SIMD" "fsqrt\\t%0., %1." [(set_attr "simd_type" "simd_fsqrt") + (set_attr "type" "neon_fp_sqrt_") (set_attr "simd_mode" "")] ) @@ -3855,6 +3941,7 @@ (define_insn "vec_load_lanesoi" "TARGET_SIMD" "ld2\\t{%S0. - %T0.}, %1" [(set_attr "simd_type" "simd_load2") + (set_attr "type" "neon_load2_2reg") (set_attr "simd_mode" "")]) (define_insn "vec_store_lanesoi" @@ -3865,6 +3952,7 @@ (define_insn "vec_store_lanesoi" "TARGET_SIMD" "st2\\t{%S1. - %T1.}, %0" [(set_attr "simd_type" "simd_store2") + (set_attr "type" "neon_store2_2reg") (set_attr "simd_mode" "")]) (define_insn "vec_load_lanesci" @@ -3875,6 +3963,7 @@ (define_insn "vec_load_lanesci" "TARGET_SIMD" "ld3\\t{%S0. - %U0.}, %1" [(set_attr "simd_type" "simd_load3") + (set_attr "type" "neon_load3_3reg") (set_attr "simd_mode" "")]) (define_insn "vec_store_lanesci" @@ -3885,6 +3974,7 @@ (define_insn "vec_store_lanesci" "TARGET_SIMD" "st3\\t{%S1. - %U1.}, %0" [(set_attr "simd_type" "simd_store3") + (set_attr "type" "neon_store3_3reg") (set_attr "simd_mode" "")]) (define_insn "vec_load_lanesxi" @@ -3895,6 +3985,7 @@ (define_insn "vec_load_lanesxi" "TARGET_SIMD" "ld4\\t{%S0. - %V0.}, %1" [(set_attr "simd_type" "simd_load4") + (set_attr "type" "neon_load4_4reg") (set_attr "simd_mode" "")]) (define_insn "vec_store_lanesxi" @@ -3905,6 +3996,7 @@ (define_insn "vec_store_lanesxi" "TARGET_SIMD" "st4\\t{%S1. - %V1.}, %0" [(set_attr "simd_type" "simd_store4") + (set_attr "type" "neon_store4_4reg") (set_attr "simd_mode" "")]) ;; Reload patterns for AdvSIMD register list operands. @@ -3938,6 +4030,8 @@ (define_insn "*aarch64_mov" } } [(set_attr "simd_type" "simd_move,simd_store,simd_load") + (set_attr "type" "neon_move,neon_store_reg_q,\ + neon_load_reg_q") (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)")) (set_attr "simd_mode" "")]) @@ -4022,6 +4116,7 @@ (define_insn "aarch64_ld2_dreg" "TARGET_SIMD" "ld2\\t{%S0. - %T0.}, %1" [(set_attr "simd_type" "simd_load2") + (set_attr "type" "neon_load2_2reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_ld2_dreg" @@ -4039,6 +4134,7 @@ (define_insn "aarch64_ld2_dreg" "TARGET_SIMD" "ld1\\t{%S0.1d - %T0.1d}, %1" [(set_attr "simd_type" "simd_load2") + (set_attr "type" "neon_load1_2reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_ld3_dreg" @@ -4061,6 +4157,7 @@ (define_insn "aarch64_ld3_dreg" "TARGET_SIMD" "ld3\\t{%S0. - %U0.}, %1" [(set_attr "simd_type" "simd_load3") + (set_attr "type" "neon_load3_3reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_ld3_dreg" @@ -4083,6 +4180,7 @@ (define_insn "aarch64_ld3_dreg" "TARGET_SIMD" "ld1\\t{%S0.1d - %U0.1d}, %1" [(set_attr "simd_type" "simd_load3") + (set_attr "type" "neon_load1_3reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_ld4_dreg" @@ -4110,6 +4208,7 @@ (define_insn "aarch64_ld4_dreg" "TARGET_SIMD" "ld4\\t{%S0. - %V0.}, %1" [(set_attr "simd_type" "simd_load4") + (set_attr "type" "neon_load4_4reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_ld4_dreg" @@ -4137,6 +4236,7 @@ (define_insn "aarch64_ld4_dreg" "TARGET_SIMD" "ld1\\t{%S0.1d - %V0.1d}, %1" [(set_attr "simd_type" "simd_load4") + (set_attr "type" "neon_load1_4reg") (set_attr "simd_mode" "")]) (define_expand "aarch64_ld" @@ -4252,6 +4352,7 @@ (define_insn "aarch64_tbl1" "TARGET_SIMD" "tbl\\t%0., {%1.16b}, %2." [(set_attr "simd_type" "simd_tbl") + (set_attr "type" "neon_tbl1") (set_attr "simd_mode" "")] ) @@ -4265,6 +4366,7 @@ (define_insn "aarch64_tbl2v16qi" "TARGET_SIMD" "tbl\\t%0.16b, {%S1.16b - %T1.16b}, %2.16b" [(set_attr "simd_type" "simd_tbl") + (set_attr "type" "neon_tbl2_q") (set_attr "simd_mode" "V16QI")] ) @@ -4280,7 +4382,9 @@ (define_insn_and_split "aarch64_combinev { aarch64_split_combinev16qi (operands); DONE; -}) +} +[(set_attr "type" "multiple")] +) (define_insn "aarch64_" [(set (match_operand:VALL 0 "register_operand" "=w") @@ -4290,6 +4394,7 @@ (define_insn "aarch64_\\t%0., %1., %2." [(set_attr "simd_type" "simd_") + (set_attr "type" "neon_permute") (set_attr "simd_mode" "")] ) @@ -4301,6 +4406,7 @@ (define_insn "aarch64_st2_dreg" "TARGET_SIMD" "st2\\t{%S1. - %T1.}, %0" [(set_attr "simd_type" "simd_store2") + (set_attr "type" "neon_store2_2reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_st2_dreg" @@ -4311,6 +4417,7 @@ (define_insn "aarch64_st2_dreg" "TARGET_SIMD" "st1\\t{%S1.1d - %T1.1d}, %0" [(set_attr "simd_type" "simd_store2") + (set_attr "type" "neon_store1_2reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_st3_dreg" @@ -4321,6 +4428,7 @@ (define_insn "aarch64_st3_dreg" "TARGET_SIMD" "st3\\t{%S1. - %U1.}, %0" [(set_attr "simd_type" "simd_store3") + (set_attr "type" "neon_store3_3reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_st3_dreg" @@ -4331,6 +4439,7 @@ (define_insn "aarch64_st3_dreg" "TARGET_SIMD" "st1\\t{%S1.1d - %U1.1d}, %0" [(set_attr "simd_type" "simd_store3") + (set_attr "type" "neon_store1_3reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_st4_dreg" @@ -4341,6 +4450,7 @@ (define_insn "aarch64_st4_dreg" "TARGET_SIMD" "st4\\t{%S1. - %V1.}, %0" [(set_attr "simd_type" "simd_store4") + (set_attr "type" "neon_store4_4reg") (set_attr "simd_mode" "")]) (define_insn "aarch64_st4_dreg" @@ -4351,6 +4461,7 @@ (define_insn "aarch64_st4_dreg" "TARGET_SIMD" "st1\\t{%S1.1d - %V1.1d}, %0" [(set_attr "simd_type" "simd_store4") + (set_attr "type" "neon_store1_4reg") (set_attr "simd_mode" "")]) (define_expand "aarch64_st" @@ -4430,6 +4541,7 @@ (define_insn "*aarch64_simd_ld1r" "TARGET_SIMD" "ld1r\\t{%0.}, %1" [(set_attr "simd_type" "simd_load1r") + (set_attr "type" "neon_load1_all_lanes") (set_attr "simd_mode" "")]) (define_insn "aarch64_frecpe" @@ -4439,6 +4551,7 @@ (define_insn "aarch64_frecpe" "TARGET_SIMD" "frecpe\\t%0., %1." [(set_attr "simd_type" "simd_frecpe") + (set_attr "type" "neon_fp_recpe_") (set_attr "simd_mode" "")] ) @@ -4449,6 +4562,7 @@ (define_insn "aarch64_frecp\\t%0, %1" [(set_attr "simd_type" "simd_frecp") + (set_attr "type" "neon_fp_recp_") (set_attr "mode" "")] ) @@ -4460,6 +4574,7 @@ (define_insn "aarch64_frecps" "TARGET_SIMD" "frecps\\t%0, %1, %2" [(set_attr "simd_type" "simd_frecps") + (set_attr "type" "neon_fp_recps_") (set_attr "simd_mode" "")] ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 13c6d958826a593dfcc54e31756ef9978dda9e4b..50bdac9b6a8ed305f76ece1b448847212b991a24 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -351,6 +351,7 @@ (define_mode_attr Vetype [(V8QI "b") (V1 (V2SI "s") (V4SI "s") (V2DI "d") (V2SF "s") (V4SF "s") (V2DF "d") + (SF "s") (DF "d") (QI "b") (HI "h") (SI "s") (DI "d")]) @@ -566,14 +567,23 @@ (define_mode_attr f [(V8QI "") (V16QI " (V2SF "f") (V4SF "f") (V2DF "f") (DF "f")]) +;; Defined to '_fp' for types whose element type is a float type. +(define_mode_attr fp [(V8QI "") (V16QI "") + (V4HI "") (V8HI "") + (V2SI "") (V4SI "") + (DI "") (V2DI "") + (V2SF "_fp") (V4SF "_fp") + (V2DF "_fp") (DF "_fp") + (SF "_fp")]) + ;; Defined to '_q' for 128-bit types. (define_mode_attr q [(V8QI "") (V16QI "_q") - (V4HI "") (V8HI "_q") - (V2SI "") (V4SI "_q") - (DI "") (V2DI "_q") - (V2SF "") (V4SF "_q") - (V2DF "_q") - (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")]) + (V4HI "") (V8HI "_q") + (V2SI "") (V4SI "_q") + (DI "") (V2DI "_q") + (V2SF "") (V4SF "_q") + (V2DF "_q") + (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")]) ;; ------------------------------------------------------------------- ;; Code Iterators