From patchwork Sat Mar 23 11:20:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Botcazou X-Patchwork-Id: 230326 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 4547D2C0085 for ; Sat, 23 Mar 2013 22:21:42 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=agT8EjIVZ0rOtXGf bSwSlDFYKPVCx8NRxHJoFsKyDm19UGACR01//2hMEH/VTvlzdCCX10J4Hj3tsCYO f0CdTAjmpfHb3J/dHoejWHSf8oLovoeCvnkWAJHTQ8Cg+uj9DQL253e/nTZaSzIL 5T/vgXI9oJcGxKjXGWrbsNaqhGE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=+yOJzTnk9DjobVYdtiYYKK Hd0ng=; b=AkFjATBgEZgqP0Uh1LI1H3pdgrs4yVeQdLQa0+3ME4LJwkePsFMIvI VzwQYp7mz0PDqshRQNjE6mpkcIckdnam0rUOHxW68Cvs/fX1CRv0jwoY3JAprBoG WrOZMG6TbEZjkldRmKGK8jIaD+Nd9ptc1tbASoa5UN1H8KEjRTgHU= Received: (qmail 10600 invoked by alias); 23 Mar 2013 11:21:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10566 invoked by uid 89); 23 Mar 2013 11:21:22 -0000 X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.1 Received: from mel.act-europe.fr (HELO mel.act-europe.fr) (194.98.77.210) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Sat, 23 Mar 2013 11:21:20 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 3B68C290014 for ; Sat, 23 Mar 2013 12:21:18 +0100 (CET) Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gVAkW25vsFlO for ; Sat, 23 Mar 2013 12:21:18 +0100 (CET) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id 111FE29000A for ; Sat, 23 Mar 2013 12:21:18 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [ARM] Fix ICE in minipool handling at -Os Date: Sat, 23 Mar 2013 12:20:35 +0100 Message-ID: <1380706.FZ55ab6V2i@polaris> User-Agent: KMail/4.7.2 (Linux/3.1.10-1.19-desktop; KDE/4.7.2; x86_64; ; ) MIME-Version: 1.0 X-Virus-Found: No We ran into an ICE at -Os on the 4.7 branch for ARM (BE/VFPv3/ARM): FAIL: gcc.c-torture/compile/920928-2.c -Os (internal compiler error) It's an assertion deep in the ARM back-end: /* If an insn doesn't have a range defined for it, then it isn't expecting to be reworked by this code. Better to stop now than to generate duff assembly code. */ gcc_assert (fix->forwards || fix->backwards); This happens for arm_zero_extendhisi2_v6, but I fail to see what is different for it from arm_extendhisi2_v6, which is expecting to be reworked. Hence the attached patch, which copies attributes from arm_extendhisi2_v6 to arm_zero_extendhisi2_v6. No regressions on ARM, OK for the mainline? 2013-03-23 Eric Botcazou * config/arm/arm.md (arm_zero_extendhisi2): Add pool_range and neg_pool_range attributes. (arm_zero_extendhisi2_v6): Likewise. Index: config/arm/arm.md =================================================================== --- config/arm/arm.md (revision 196816) +++ config/arm/arm.md (working copy) @@ -4650,7 +4650,9 @@ (define_insn "*arm_zero_extendhisi2" # ldr%(h%)\\t%0, %1" [(set_attr "type" "alu_shift,load_byte") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] ) (define_insn "*arm_zero_extendhisi2_v6" @@ -4660,8 +4662,10 @@ (define_insn "*arm_zero_extendhisi2_v6" "@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "type" "simple_alu_shift,load_byte")] + [(set_attr "type" "simple_alu_shift,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] ) (define_insn "*arm_zero_extendhisi2addsi"