From patchwork Fri Sep 6 13:46:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 273202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "www.sourceware.org", Issuer "StartCom Class 1 Primary Intermediate Server CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 31B4B2C00EB for ; Fri, 6 Sep 2013 23:46:24 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=yOLwbbcdEnntYYd6+CgtxyxxbF1+HrhJ/Vx7QtUQwxvHtnw+oT LjBgxyyToCgEeXVIbaXDip7HJ6xLwJTtMhiSnTm3runwovxcH+lEslFb3Jt3oQfx EcT8VQuD6Sf3z0ovkel77tfC19CTtYU1vJr0RRwwwrl97mvYJS5GiUchI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=6Tpqn5WeVWsfDWI7mWX/2zYpKfk=; b=aS59rN4Z7O2PUliyY0ZM 6I6XQBJfhamoQVMXzq2EtiCIP1y56IJVT3chsNQpzEGClaN6iohz7SjDNMDLxiY2 Ot0AzHwfAZs/Pqi73vVlTuCCHUqdcAK7vwG54V0ImrXbjGluKsgjz6iMmrK5YnaT 3YfaVL3C+FmLKp13CpU4Rjw= Received: (qmail 30727 invoked by alias); 6 Sep 2013 13:46:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30718 invoked by uid 89); 6 Sep 2013 13:46:18 -0000 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 06 Sep 2013 13:46:18 +0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_NO, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 06 Sep 2013 14:46:15 +0100 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Fri, 6 Sep 2013 14:46:14 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com, richard.earnshaw@arm.com, ramana.radhakrishnan@arm.com Subject: [AArch64] Use "multiple" for type, where more than one instruction is used for a move Date: Fri, 6 Sep 2013 14:46:10 +0100 Message-Id: <1378475170-8477-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113090614461501101 X-IsSubscribed: yes Hi, We could introduce a whole new type for insns which generate two moves, but we have already introduced a "multiple" classification for types in the ARM backend, so use that in place of "mov_reg" where appropriate. Regression tested on aarch64-none-elf and arm-none-eabi with no regressions. OK? Thanks, James --- gcc/ 2013-09-06 James Greenhalgh * config/aarch64/aarch64.md (*movti_aarch64): Use "multiple" for type where v8type is "move2". (*movtf_aarch64): Likewise. * config/arm/arm.md (thumb1_movdi_insn): Use "multiple" for type where more than one instruction is used for a move. (*arm32_movhf): Likewise. (*thumb_movdf_insn): Likewise. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index db6aa1d3fa15e17095ba26a64e020d098e9fa6c0..96705862de6b53322828fd60df15207af4b2ed61 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -906,7 +906,7 @@ (define_insn "*movti_aarch64" str\\t%q1, %0" [(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \ load2,store2,store2,fpsimd_load,fpsimd_store") - (set_attr "type" "mov_reg,f_mcr,f_mrc,*, \ + (set_attr "type" "multiple,f_mcr,f_mrc,*, \ load2,store2,store2,f_loadd,f_stored") (set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*") (set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI") @@ -1024,7 +1024,7 @@ (define_insn "*movtf_aarch64" ldp\\t%0, %H0, %1 stp\\t%1, %H1, %0" [(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2") - (set_attr "type" "logic_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\ + (set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\ f_loadd,f_stored,f_loadd,f_stored") (set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF") (set_attr "length" "4,8,8,8,4,4,4,4,4,4") diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 6c0fbf44288c9f6e077fe2d9836cd5c1e2042a0a..fd0b1cbdccd23ad4d18be50417c7532b29840b91 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6141,7 +6141,7 @@ (define_insn "*thumb1_movdi_insn" } }" [(set_attr "length" "4,4,6,2,2,6,4,4") - (set_attr "type" "multiple,mov_reg,multiple,load2,store2,load2,store2,mov_reg") + (set_attr "type" "multiple,multiple,multiple,load2,store2,load2,store2,multiple") (set_attr "pool_range" "*,*,*,*,*,1018,*,*")] ) @@ -7221,7 +7221,7 @@ (define_insn "*arm32_movhf" } " [(set_attr "conds" "unconditional") - (set_attr "type" "load1,store1,mov_reg,mov_reg") + (set_attr "type" "load1,store1,mov_reg,multiple") (set_attr "length" "4,4,4,8") (set_attr "predicable" "yes")] ) @@ -7466,7 +7466,7 @@ (define_insn "*thumb_movdf_insn" } " [(set_attr "length" "4,2,2,6,4,4") - (set_attr "type" "multiple,load2,store2,load2,store2,mov_reg") + (set_attr "type" "multiple,load2,store2,load2,store2,multiple") (set_attr "pool_range" "*,*,*,1018,*,*")] )