From patchwork Thu Aug 29 18:45:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleg Endo X-Patchwork-Id: 270891 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "www.sourceware.org", Issuer "StartCom Class 1 Primary Intermediate Server CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id B7FA12C0091 for ; Fri, 30 Aug 2013 04:45:56 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:in-reply-to:references :content-type:mime-version; q=dns; s=default; b=PwdgcFEk4WOrm+Kd +bBb+6fyuoa2icI62q3E3aQ42ZXXWky3GyAkvx/Hkwu0juOAL+kbFUjndMUmS53N UymyIh5vssPZPYiaDT2gZ9ATWrBszSpTRCqZwlRak32nFPlGa3P9/VEoK19HKaRa 2wqYYB86HX0n1LsO0POg3LusogY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:in-reply-to:references :content-type:mime-version; s=default; bh=HIFDWnowlX/YNBw4qz+vGg Kmk3M=; b=RRaP5gtxRDZtuayQH+PurH+xoTWoqZ6gTVDuBiIZbSRg4+eYF4r5e8 KqMo+u/dge/fBSEkWgQJXDkxoI3X8BfXrUZr2d2NN9SdeQ9PbX1MZh2E26qDOJrT 10FWuOKN7qd6UYsQJEkTMDSVtd1QwaACBxNaToBxoGtRB7xzsFIMg= Received: (qmail 29419 invoked by alias); 29 Aug 2013 18:45:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 29406 invoked by uid 89); 29 Aug 2013 18:45:49 -0000 Received: from mailout06.t-online.de (HELO mailout06.t-online.de) (194.25.134.19) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Aug 2013 18:45:49 +0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL, BAYES_00, HELO_MISC_IP, KHOP_THREADED, RCVD_IN_PBL, RCVD_IN_SEMBLACK, UNPARSEABLE_RELAY autolearn=no version=3.3.2 X-HELO: mailout06.t-online.de Received: from fwd53.aul.t-online.de (fwd53.aul.t-online.de ) by mailout06.t-online.de with smtp id 1VF7Dr-0004ml-LQ; Thu, 29 Aug 2013 20:45:35 +0200 Received: from [192.168.0.103] (STIg+TZBrhayc1SNdAkCu-vS8pBcgW-1V4cJ4jNl2pxdpn-p6ywhlOhe6NXd3ODgH3@[93.195.26.52]) by fwd53.t-online.de with esmtp id 1VF7Dq-0pJXrE0; Thu, 29 Aug 2013 20:45:34 +0200 Message-ID: <1377801933.16741.3.camel@yam-132-YW-E178-FTW> Subject: Re: [PATCH] Fix illegal cast to rtx (*insn_gen_fn) (rtx, ...) From: Oleg Endo To: Michael Meissner Cc: Richard Henderson , Uros Bizjak , "gcc-patches@gcc.gnu.org" , Stefan Kristiansson , Andreas Schwab Date: Thu, 29 Aug 2013 20:45:33 +0200 In-Reply-To: <1375903499.3952.89.camel@yam-132-YW-E178-FTW> References: <1374929541.2368.76.camel@yam-132-YW-E178-FTW> <52001C5F.5080809@redhat.com> <1375741943.3952.69.camel@yam-132-YW-E178-FTW> <52003462.2090500@redhat.com> <1375825540.3952.87.camel@yam-132-YW-E178-FTW> <20130807190820.GA12791@ibm-tiger.the-meissners.org> <1375903499.3952.89.camel@yam-132-YW-E178-FTW> Mime-Version: 1.0 On Wed, 2013-08-07 at 21:24 +0200, Oleg Endo wrote: > On Wed, 2013-08-07 at 15:08 -0400, Michael Meissner wrote: > > On Tue, Aug 06, 2013 at 11:45:40PM +0200, Oleg Endo wrote: > > > On Mon, 2013-08-05 at 13:25 -1000, Richard Henderson wrote: > > > > On 08/05/2013 12:32 PM, Oleg Endo wrote: > > > > > Thanks, committed as rev 201513. > > > > > 4.8 also has the same problem. The patch applies on 4.8 branch without > > > > > problems and make all-gcc works. > > > > > OK for 4.8, too? > > > > > > > > Hum. I suppose so, since it's relatively self-contained. I suppose the > > > > out-of-tree openrisc port will thank us... > > > > > > Maybe it's better to wait for a while and collect follow up patches such > > > as the rs6000 one. > > > > The tree right now is broken for the powerpc. I would prefer to get patches > > installed ASAP rather than waiting for additional ports. > > I've just committed the PPC fix for trunk. Sorry for the delay. > I haven't committed anything related to this issue on the 4.8 branch > yet. I'll do that next week if nothing else comes up. Sorry for the delay. I've just backported the 2 patches to 4.8. Tested with 'make all-gcc' for SH and PPC cross compilers. Committed as rev 202083. Cheers, Oleg Index: gcc/expr.c =================================================================== --- gcc/expr.c (revision 202080) +++ gcc/expr.c (working copy) @@ -119,7 +119,7 @@ int reverse; }; -static void move_by_pieces_1 (rtx (*) (rtx, ...), enum machine_mode, +static void move_by_pieces_1 (insn_gen_fn, machine_mode, struct move_by_pieces_d *); static bool block_move_libcall_safe_for_call_parm (void); static bool emit_block_move_via_movmem (rtx, rtx, rtx, unsigned, unsigned, HOST_WIDE_INT); @@ -128,7 +128,7 @@ static rtx clear_by_pieces_1 (void *, HOST_WIDE_INT, enum machine_mode); static void clear_by_pieces (rtx, unsigned HOST_WIDE_INT, unsigned int); static void store_by_pieces_1 (struct store_by_pieces_d *, unsigned int); -static void store_by_pieces_2 (rtx (*) (rtx, ...), enum machine_mode, +static void store_by_pieces_2 (insn_gen_fn, machine_mode, struct store_by_pieces_d *); static tree clear_storage_libcall_fn (int); static rtx compress_float_constant (rtx, rtx); @@ -1043,7 +1043,7 @@ to make a move insn for that mode. DATA has all the other info. */ static void -move_by_pieces_1 (rtx (*genfun) (rtx, ...), enum machine_mode mode, +move_by_pieces_1 (insn_gen_fn genfun, machine_mode mode, struct move_by_pieces_d *data) { unsigned int size = GET_MODE_SIZE (mode); @@ -2657,7 +2657,7 @@ to make a move insn for that mode. DATA has all the other info. */ static void -store_by_pieces_2 (rtx (*genfun) (rtx, ...), enum machine_mode mode, +store_by_pieces_2 (insn_gen_fn genfun, machine_mode mode, struct store_by_pieces_d *data) { unsigned int size = GET_MODE_SIZE (mode); Index: gcc/recog.h =================================================================== --- gcc/recog.h (revision 202080) +++ gcc/recog.h (working copy) @@ -256,8 +256,58 @@ typedef int (*insn_operand_predicate_fn) (rtx, enum machine_mode); typedef const char * (*insn_output_fn) (rtx *, rtx); -typedef rtx (*insn_gen_fn) (rtx, ...); +struct insn_gen_fn +{ + typedef rtx (*f0) (void); + typedef rtx (*f1) (rtx); + typedef rtx (*f2) (rtx, rtx); + typedef rtx (*f3) (rtx, rtx, rtx); + typedef rtx (*f4) (rtx, rtx, rtx, rtx); + typedef rtx (*f5) (rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f6) (rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f7) (rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f8) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f9) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f10) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f11) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f12) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f13) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f14) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f15) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + typedef rtx (*f16) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx); + + typedef f0 stored_funcptr; + + rtx operator () (void) const { return ((f0)func) (); } + rtx operator () (rtx a0) const { return ((f1)func) (a0); } + rtx operator () (rtx a0, rtx a1) const { return ((f2)func) (a0, a1); } + rtx operator () (rtx a0, rtx a1, rtx a2) const { return ((f3)func) (a0, a1, a2); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3) const { return ((f4)func) (a0, a1, a2, a3); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4) const { return ((f5)func) (a0, a1, a2, a3, a4); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5) const { return ((f6)func) (a0, a1, a2, a3, a4, a5); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6) const { return ((f7)func) (a0, a1, a2, a3, a4, a5, a6); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7) const { return ((f8)func) (a0, a1, a2, a3, a4, a5, a6, a7); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7, rtx a8) const { return ((f9)func) (a0, a1, a2, a3, a4, a5, a6, a7, a8); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7, rtx a8, rtx a9) const { return ((f10)func) (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7, rtx a8, rtx a9, rtx a10) const { return ((f11)func) (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7, rtx a8, rtx a9, rtx a10, rtx a11) const { return ((f12)func) (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7, rtx a8, rtx a9, rtx a10, rtx a11, rtx a12) const { return ((f13)func) (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7, rtx a8, rtx a9, rtx a10, rtx a11, rtx a12, rtx a13) const { return ((f14)func) (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7, rtx a8, rtx a9, rtx a10, rtx a11, rtx a12, rtx a13, rtx a14) const { return ((f15)func) (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14); } + rtx operator () (rtx a0, rtx a1, rtx a2, rtx a3, rtx a4, rtx a5, rtx a6, rtx a7, rtx a8, rtx a9, rtx a10, rtx a11, rtx a12, rtx a13, rtx a14, rtx a15) const { return ((f16)func) (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15); } + + // This is for compatibility of code that invokes functions like + // (*funcptr) (arg) + insn_gen_fn operator * (void) const { return *this; } + + // The wrapped function pointer must be public and there must not be any + // constructors. Otherwise the insn_data_d struct initializers generated + // by genoutput.c will result in static initializer functions, which defeats + // the purpose of the generated insn_data_d array. + stored_funcptr func; +}; + struct insn_operand_data { const insn_operand_predicate_fn predicate; Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 202080) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -284,9 +284,6 @@ { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) }, }; -/* 2 argument gen function typedef. */ -typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx); - /* Pointer to function (in rs6000-c.c) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.c, so we can't call it directly. */ @@ -26657,7 +26654,7 @@ enum machine_mode mode = GET_MODE (dst); rtx x0, e0, e1, y1, u0, v0; enum insn_code code = optab_handler (smul_optab, mode); - gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code); + insn_gen_fn gen_mul = GEN_FCN (code); rtx one = rs6000_load_constant_and_splat (mode, dconst1); gcc_assert (code != CODE_FOR_nothing); @@ -26695,7 +26692,7 @@ enum machine_mode mode = GET_MODE (dst); rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one; enum insn_code code = optab_handler (smul_optab, mode); - gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code); + insn_gen_fn gen_mul = GEN_FCN (code); gcc_assert (code != CODE_FOR_nothing); @@ -26766,7 +26763,7 @@ int i; rtx halfthree; enum insn_code code = optab_handler (smul_optab, mode); - gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code); + insn_gen_fn gen_mul = GEN_FCN (code); gcc_assert (code != CODE_FOR_nothing); Index: gcc/genoutput.c =================================================================== --- gcc/genoutput.c (revision 202080) +++ gcc/genoutput.c (working copy) @@ -404,9 +404,9 @@ } if (d->name && d->name[0] != '*') - printf (" (insn_gen_fn) gen_%s,\n", d->name); + printf (" { (insn_gen_fn::stored_funcptr) gen_%s },\n", d->name); else - printf (" 0,\n"); + printf (" { 0 },\n"); printf (" &operand_data[%d],\n", d->operand_number); printf (" %d,\n", d->n_generator_args);