From patchwork Tue Nov 6 04:54:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Bergner X-Patchwork-Id: 197405 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 5BD862C00B5 for ; Tue, 6 Nov 2012 15:55:14 +1100 (EST) Comment: DKIM? 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Violators will be prosecuted; Mon, 5 Nov 2012 23:54:39 -0500 Received: from d01relay07.pok.ibm.com (d01relay07.pok.ibm.com [9.56.227.147]) by d01dlp02.pok.ibm.com (Postfix) with ESMTP id DA6176E8036 for ; Mon, 5 Nov 2012 23:54:38 -0500 (EST) Received: from d01av04.pok.ibm.com (d01av04.pok.ibm.com [9.56.224.64]) by d01relay07.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id qA64scEF63897766 for ; Mon, 5 Nov 2012 23:54:38 -0500 Received: from d01av04.pok.ibm.com (loopback [127.0.0.1]) by d01av04.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id qA64sbHv009559 for ; Mon, 5 Nov 2012 23:54:37 -0500 Received: from [192.168.1.113] (vorma.rchland.ibm.com [9.10.86.174]) by d01av04.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id qA64sZ7e009444; Mon, 5 Nov 2012 23:54:35 -0500 Subject: [PATCH] Enable -mcpu=power8 for PowerPC From: Peter Bergner To: "gcc-patches@gcc.gnu.org" Cc: Michael Meissner , David Edelsohn Date: Mon, 05 Nov 2012 22:54:35 -0600 Message-ID: <1352177675.4636.34.camel@otta> Mime-Version: 1.0 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12110604-3534-0000-0000-00000EA8D628 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This patch enables new -mcpu and -mtune options for POWER8. The -mcpu=power8 option currently is just an alias for power7. The affect of these options will be expanded when more technical details are released by IBM. Bootstrapped and regtested on powerpc64-linux. Ok for mainline or should we wait to commit this after stage1 (since Jakub said it was ok in another thread) when we commit our base power8 patches? Peter * doc/invoke.texi (-mcpu=power8): Document. * config.in (HAVE_AS_POWER8): New. * config.gcc: Add cpu_type power8. * configure.ac: (HAVE_AS_POWER8): Check for assembler support for the POWER8 instructions. * configure: Regenerate. * config/rs6000/rs6000.h: (ASM_CPU_POWER8_SPEC): Define. (ASM_CPU_SPEC): Pass %(asm_cpu_power8) for -mcpu=power8. (EXTRA_SPECS): Add asm_cpu_power8 spec string. * config/rs6000/rs6000-cpus.def (processor_target_table): Alias POWER8 to POWER7. * config/rs6000/driver-rs6000.c (ASM_CPU_SPEC): For -mcpu=power8, pass %(asm_cpu_power8)/-mpwr8. * config/rs6000/aix53.h: Likewise. * config/rs6000/aix61.h: Likewise. Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 193151) +++ gcc/doc/invoke.texi (working copy) @@ -17086,7 +17086,7 @@ @samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500}, @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, -@samp{power6}, @samp{power6x}, @samp{power7}, @samp{powerpc}, +@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, @samp{powerpc}, @samp{powerpc64}, and @samp{rs64}. @option{-mcpu=powerpc}, and @option{-mcpu=powerpc64} specify pure 32-bit @@ -17888,9 +17888,9 @@ @opindex mrecip-precision Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC -ABI. Selecting @option{-mcpu=power6} or @option{-mcpu=power7} -automatically selects @option{-mrecip-precision}. The double-precision -square root estimate instructions are not generated by +ABI. Selecting @option{-mcpu=power6}, @option{-mcpu=power7} or +@option{-mcpu=power8} automatically selects @option{-mrecip-precision}. +The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an estimate that converges after three steps. Index: gcc/config.in =================================================================== --- gcc/config.in (revision 193151) +++ gcc/config.in (working copy) @@ -441,6 +441,12 @@ #endif +/* Define if your assembler supports POWER8 instructions. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_POWER8 +#endif + + /* Define if your assembler supports .ref */ #ifndef USED_FOR_TARGET #undef HAVE_AS_REF Index: gcc/configure.ac =================================================================== --- gcc/configure.ac (revision 193151) +++ gcc/configure.ac (working copy) @@ -3864,6 +3864,19 @@ [Define if your assembler supports POPCNTD instructions.])]) case $target in + *-*-aix*) conftest_s=' .machine "pwr8" + .csect .text[[PR]]';; + *) conftest_s=' .machine power8 + .text';; + esac + + gcc_GAS_CHECK_FEATURE([power8 support], + gcc_cv_as_powerpc_power8, [2,19,2], -a32, + [$conftest_s],, + [AC_DEFINE(HAVE_AS_POWER8, 1, + [Define if your assembler supports POWER8 instructions.])]) + + case $target in *-*-aix*) conftest_s=' .csect .text[[PR]] lwsync';; *) conftest_s=' .text Index: gcc/config.gcc =================================================================== --- gcc/config.gcc (revision 193151) +++ gcc/config.gcc (working copy) @@ -424,7 +424,7 @@ extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h" need_64bit_hwint=yes case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500) + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[345678]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500) cpu_is_64bit=yes ;; esac @@ -3460,7 +3460,7 @@ eval "with_$which=405" ;; "" | common \ - | power | power[234567] | power6x | powerpc | powerpc64 \ + | power | power[2345678] | power6x | powerpc | powerpc64 \ | rios | rios1 | rios2 | rsc | rsc1 | rs64a \ | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \ Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 193151) +++ gcc/config/rs6000/aix53.h (working copy) @@ -62,6 +62,7 @@ %{mcpu=power6: -mpwr6} \ %{mcpu=power6x: -mpwr6} \ %{mcpu=power7: -mpwr7} \ +%{mcpu=power8: -mpwr8} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rs64a: -mppc} \ %{mcpu=603: -m603} \ Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 193151) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -89,6 +89,12 @@ #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" #endif +#ifdef HAVE_AS_POWER8 +#define ASM_CPU_POWER8_SPEC "-mpower8" +#else +#define ASM_CPU_POWER8_SPEC "-mpower4 -maltivec" +#endif + #ifdef HAVE_AS_DCI #define ASM_CPU_476_SPEC "-m476" #else @@ -112,6 +118,7 @@ %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ %{mcpu=power7: %(asm_cpu_power7)} \ +%{mcpu=power8: %(asm_cpu_power8)} \ %{mcpu=a2: -ma2} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rs64a: -mppc64} \ @@ -184,6 +191,7 @@ { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ + { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ { "asm_cpu_476", ASM_CPU_476_SPEC }, \ SUBTARGET_EXTRA_SPECS Index: gcc/config/rs6000/aix61.h =================================================================== --- gcc/config/rs6000/aix61.h (revision 193151) +++ gcc/config/rs6000/aix61.h (working copy) @@ -62,6 +62,7 @@ %{mcpu=power6: -mpwr6} \ %{mcpu=power6x: -mpwr6} \ %{mcpu=power7: -mpwr7} \ +%{mcpu=power8: -mpwr8} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rs64a: -mppc} \ %{mcpu=603: -m603} \ Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 193151) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -166,6 +166,10 @@ POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD | MASK_VSX | MASK_RECIP_PRECISION) +RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ + POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF + | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD + | MASK_VSX | MASK_RECIP_PRECISION) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) Index: gcc/config/rs6000/driver-rs6000.c =================================================================== --- gcc/config/rs6000/driver-rs6000.c (revision 193151) +++ gcc/config/rs6000/driver-rs6000.c (working copy) @@ -354,6 +354,7 @@ { "power6", "-mpwr6" }, { "power6x", "-mpwr6" }, { "power7", "-mpwr7" }, + { "power8", "-mpwr8" }, { "powerpc", "-mppc" }, { "rs64a", "-mppc" }, { "603", "-m603" }, @@ -379,6 +380,7 @@ { "power6", "%(asm_cpu_power6) -maltivec" }, { "power6x", "%(asm_cpu_power6) -maltivec" }, { "power7", "%(asm_cpu_power7)" }, + { "power8", "%(asm_cpu_power8)" }, { "powerpc", "-mppc" }, { "rs64a", "-mppc64" }, { "401", "-mppc" },