| Message ID | 1338264799-12374-2-git-send-email-mattst88@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 29 May 2012 05:13, Matt Turner <mattst88@gmail.com> wrote: > From: Xinyu Qi <xyqi@marvell.com> > > gcc/ > * config/arm/arm.c (FL_IWMMXT2): New define. > (arm_arch_iwmmxt2): New variable. > (arm_option_override): Enable use of iWMMXt with VFP. > Disable use of iWMMXt with NEON. Disable use of iWMMXt under > Thumb mode. Set arm_arch_iwmmxt2. > (arm_expand_binop_builtin): Accept VOIDmode op. > * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __IWMMXT2__. > (TARGET_IWMMXT2): New define. > (TARGET_REALLY_IWMMXT2): Likewise. > (arm_arch_iwmmxt2): Declare. > * config/arm/arm-cores.def (iwmmxt2): Add FL_IWMMXT2. > * config/arm/arm-arches.def (iwmmxt2): Likewise. > * config/arm/arm.md (arch): Add "iwmmxt2". > (arch_enabled): Handle "iwmmxt2". > --- > gcc/config/arm/arm-arches.def | 2 +- > gcc/config/arm/arm-cores.def | 2 +- > gcc/config/arm/arm.c | 25 +++++++++++++++++-------- > gcc/config/arm/arm.h | 7 +++++++ > gcc/config/arm/arm.md | 6 +++++- > 5 files changed, 31 insertions(+), 11 deletions(-) > > diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def > index 3123426..f4dd6cc 100644 > --- a/gcc/config/arm/arm-arches.def > +++ b/gcc/config/arm/arm-arches.def > @@ -57,4 +57,4 @@ ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M) > ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM) > ARM_ARCH("ep9312", ep9312, 4T, FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4) > ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT) > -ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT) > +ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2) > diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def > index d82b10b..c82eada 100644 > --- a/gcc/config/arm/arm-cores.def > +++ b/gcc/config/arm/arm-cores.def > @@ -105,7 +105,7 @@ ARM_CORE("arm1020e", arm1020e, 5TE, FL_LDSCHED, fastmul) > ARM_CORE("arm1022e", arm1022e, 5TE, FL_LDSCHED, fastmul) > ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale) > ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) > -ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) > +ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2, xscale) > ARM_CORE("fa606te", fa606te, 5TE, FL_LDSCHED, 9e) > ARM_CORE("fa626te", fa626te, 5TE, FL_LDSCHED, 9e) > ARM_CORE("fmp626", fmp626, 5TE, FL_LDSCHED, 9e) > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 7a98197..b0680ab 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -685,6 +685,7 @@ static int thumb_call_reg_needed; > #define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ > > #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ > +#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ > > /* Flags that only effect tuning, not available instructions. */ > #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ > @@ -766,6 +767,9 @@ int arm_arch_cirrus = 0; > /* Nonzero if this chip supports Intel Wireless MMX technology. */ > int arm_arch_iwmmxt = 0; > > +/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ > +int arm_arch_iwmmxt2 = 0; > + > /* Nonzero if this chip is an XScale. */ > int arm_arch_xscale = 0; > > @@ -1717,6 +1721,7 @@ arm_option_override (void) > arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; > arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; > arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; > + arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0; > arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0; > arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0; > arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; > @@ -1817,14 +1822,17 @@ arm_option_override (void) > } > > /* FPA and iWMMXt are incompatible because the insn encodings overlap. > - VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon > - will ever exist. GCC makes no attempt to support this combination. */ > - if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) > - sorry ("iWMMXt and hardware floating point"); > + VFP and iWMMXt however can coexist. */ > + if (TARGET_IWMMXT && TARGET_HARD_FLOAT && !TARGET_VFP) > + error ("iWMMXt and non-VFP floating point unit are incompatible"); > + > + /* iWMMXt and NEON are incompatible. */ > + if (TARGET_IWMMXT && TARGET_NEON) > + error ("iWMMXt and NEON are incompatible"); > > - /* ??? iWMMXt insn patterns need auditing for Thumb-2. */ > - if (TARGET_THUMB2 && TARGET_IWMMXT) > - sorry ("Thumb-2 iWMMXt"); > + /* iWMMXt unsupported under Thumb mode. */ > + if (TARGET_THUMB && TARGET_IWMMXT) > + error ("iWMMXt unsupported under Thumb mode"); > > /* __fp16 support currently assumes the core has ldrh. */ > if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE) > @@ -20867,7 +20875,8 @@ arm_expand_binop_builtin (enum insn_code icode, > || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) > target = gen_reg_rtx (tmode); > > - gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); > + gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode) > + && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode)); > > if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) > op0 = copy_to_mode_reg (mode0, op0); > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h > index f4204e4..c51bce9 100644 > --- a/gcc/config/arm/arm.h > +++ b/gcc/config/arm/arm.h > @@ -97,6 +97,8 @@ extern char arm_arch_name[]; > builtin_define ("__XSCALE__"); \ > if (arm_arch_iwmmxt) \ > builtin_define ("__IWMMXT__"); \ > + if (arm_arch_iwmmxt2) \ > + builtin_define ("__IWMMXT2__"); \ > if (TARGET_AAPCS_BASED) \ > { \ > if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ > @@ -194,7 +196,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void); > #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK) > #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) > #define TARGET_IWMMXT (arm_arch_iwmmxt) > +#define TARGET_IWMMXT2 (arm_arch_iwmmxt2) > #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) > +#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) > #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) > #define TARGET_ARM (! TARGET_THUMB) > #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ > @@ -410,6 +414,9 @@ extern int arm_arch_cirrus; > /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ > extern int arm_arch_iwmmxt; > > +/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ > +extern int arm_arch_iwmmxt2; > + > /* Nonzero if this chip is an XScale. */ > extern int arm_arch_xscale; > > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index bbf6380..ad9d948 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -197,7 +197,7 @@ > ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without > ; arm_arch6. This attribute is used to compute attribute "enabled", > ; use type "any" to enable an alternative in all cases. > -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8" > +(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8,iwmmxt,iwmmxt2" > (const_string "any")) > > (define_attr "arch_enabled" "no,yes" > @@ -248,6 +248,10 @@ > (and (eq_attr "arch" "neon_nota8") > (not (eq_attr "tune" "cortexa8")) > (match_test "TARGET_NEON")) > + (const_string "yes") > + Unnecessary new line here. > + (and (eq_attr "arch" "iwmmxt2") > + (match_test "TARGET_REALLY_IWMMXT2")) > (const_string "yes")] > (const_string "no"))) Given that we already have iwmmxt2 as a CPU it isn't really changing behaviour. OK with that change. regards, Ramana > > -- > 1.7.3.4 >
Ping, Fix ChangeLog * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. * config/arm/iwmmxt.md (WCGR0): Update. (WCGR1, WCGR2, WCGR3): Likewise. > Hi, > > It is necessary to sync the constants WCGR0 to WCGR3 in iwmmxt.md with > the IWMMXT_GR_REGNUM in arm.h. > > ChangeLog > * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. > * config/arm/iwmmxt.md (WCGR0, WCGR1): Update. > * config/arm/iwmmxt.md (WCGR2, WCGR3): Likewise. > > Index: config/arm/arm.h > ================================================================ > === > --- config/arm/arm.h (revision 194603) > +++ config/arm/arm.h (working copy) > @@ -947,6 +947,8 @@ > > #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) > #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) > + > +/* Need to sync with WCGR in iwmmxt.md. */ > #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) > #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + > 3) > > Index: config/arm/iwmmxt.md > ================================================================ > === > --- config/arm/iwmmxt.md (revision 194603) > +++ config/arm/iwmmxt.md (working copy) > @@ -19,12 +19,12 @@ > ;; along with GCC; see the file COPYING3. If not see ;; > <http://www.gnu.org/licenses/>. > > -;; Register numbers > +;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in > arm.h > (define_constants > - [(WCGR0 43) > - (WCGR1 44) > - (WCGR2 45) > - (WCGR3 46) > + [(WCGR0 96) > + (WCGR1 97) > + (WCGR2 98) > + (WCGR3 99) > ] > ) > > > OK? > > Thanks, > Xinyu
On 01/22/13 09:21, Xinyu Qi wrote: > Ping, > > Fix ChangeLog The ChangeLog format includes . <date> <Author's name> <a.b@c.com> If you want a patch accepted in the future, please help by creating the Changelog entry in the correct format, i.e. fill in the author's name as well as email address as below. I've created an entry as below. Please remember to do so for every patch you submit - thanks. <DATE> Xinyu Qi <xyqi@marvell.com> * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. * config/arm/iwmmxt.md (WCGR0): Update. (WCGR1, WCGR2, WCGR3): Likewise. The patch by itself is OK but surprisingly I never saw this earlier. Your ping has removed the date from the original post so I couldn't track it down. Anyway, please apply. regards, Ramana
Ramana Radhakrishnan <ramrad01@arm.com> writes: > The patch by itself is OK but surprisingly I never saw this earlier. Your > ping has removed the date from the original post so I couldn't track it > down. You can follow the references and look up the message-id via http://mid.gmane.org/<msg-id>. Andreas.
At 2013-01-22 19:58:43,"Ramana Radhakrishnan" <ramrad01@arm.com> wrote: > On 01/22/13 09:21, Xinyu Qi wrote: > > Ping, > > > > Fix ChangeLog > > The ChangeLog format includes . > > <date> <Author's name> <a.b@c.com> > > If you want a patch accepted in the future, please help by creating the > Changelog entry in the correct format, i.e. fill in the author's name as well as > email address as below. I've created an entry as below. Please remember to do > so for every patch you submit - thanks. > > <DATE> Xinyu Qi <xyqi@marvell.com> > > * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. > * config/arm/iwmmxt.md (WCGR0): Update. > (WCGR1, WCGR2, WCGR3): Likewise. > > The patch by itself is OK but surprisingly I never saw this earlier. > Your ping has removed the date from the original post so I couldn't track it > down. Hi Ramana, Thanks for reviewing. I forget to keep the date which shows the original post is at Wed, 26 Dec 2012 You can find it at http://gcc.gnu.org/ml/gcc-patches/2012-12/msg01418.html I would remember to set the correct Changelog entry next time. > > Anyway, please apply. BTW, since I have no write access, would you mind to help to check in this patch? Thanks! Xinyu > > > regards, > Ramana > >
At 2013-01-22 19:58:43,"Ramana Radhakrishnan" <ramrad01@arm.com> wrote:> > On 01/22/13 09:21, Xinyu Qi wrote: > > Ping, > > > > Fix ChangeLog > > The ChangeLog format includes . > > <date> <Author's name> <a.b@c.com> > > If you want a patch accepted in the future, please help by creating the > Changelog entry in the correct format, i.e. fill in the author's name as well as > email address as below. I've created an entry as below. Please remember to do > so for every patch you submit - thanks. > > <DATE> Xinyu Qi <xyqi@marvell.com> > > * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. > * config/arm/iwmmxt.md (WCGR0): Update. > (WCGR1, WCGR2, WCGR3): Likewise. > > The patch by itself is OK but surprisingly I never saw this earlier. > Your ping has removed the date from the original post so I couldn't track it > down. > > Anyway, please apply. > > > regards, > Ramana > > Hi Nick, Since I have no write access, would you mind to help to check in this patch which has already been approved? The patch is attached. ChangeLog 2013-01-31 Xinyu Qi <xyqi@marvell.com> * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. * config/arm/iwmmxt.md (WCGR0): Update. (WCGR1, WCGR2, WCGR3): Likewise. Thanks, Xinyu
>At 2013-01-22 19:58:43,"Ramana Radhakrishnan" <ramrad01@arm.com> wrote:> > > On 01/22/13 09:21, Xinyu Qi wrote: > > > Ping, > > > > > > Fix ChangeLog > > > > The ChangeLog format includes . > > > > <date> <Author's name> <a.b@c.com> > > > > If you want a patch accepted in the future, please help by creating > > the Changelog entry in the correct format, i.e. fill in the author's > > name as well as email address as below. I've created an entry as > > below. Please remember to do so for every patch you submit - thanks. > > > > <DATE> Xinyu Qi <xyqi@marvell.com> > > > > * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. > > * config/arm/iwmmxt.md (WCGR0): Update. > > (WCGR1, WCGR2, WCGR3): Likewise. > > > > The patch by itself is OK but surprisingly I never saw this earlier. > > Your ping has removed the date from the original post so I couldn't > > track it down. > > > > Anyway, please apply. > > > > > > regards, > > Ramana > > > > > Hi Ramana, Since I have no write access, would you mind to help to check in this patch? The patch is attached. ChangeLog 2013-01-31 Xinyu Qi <xyqi@marvell.com> * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. * config/arm/iwmmxt.md (WCGR0): Update. (WCGR1, WCGR2, WCGR3): Likewise. Thanks, Xinyu
On Wed, Mar 20, 2013 at 2:43 AM, Xinyu Qi <xyqi@marvell.com> wrote: >>At 2013-01-22 19:58:43,"Ramana Radhakrishnan" <ramrad01@arm.com> wrote:> >> > On 01/22/13 09:21, Xinyu Qi wrote: >> > > Ping, >> > > >> > > Fix ChangeLog >> > >> > The ChangeLog format includes . >> > >> > <date> <Author's name> <a.b@c.com> >> > >> > If you want a patch accepted in the future, please help by creating >> > the Changelog entry in the correct format, i.e. fill in the author's >> > name as well as email address as below. I've created an entry as >> > below. Please remember to do so for every patch you submit - thanks. >> > >> > <DATE> Xinyu Qi <xyqi@marvell.com> >> > >> > * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. >> > * config/arm/iwmmxt.md (WCGR0): Update. >> > (WCGR1, WCGR2, WCGR3): Likewise. >> > >> > The patch by itself is OK but surprisingly I never saw this earlier. >> > Your ping has removed the date from the original post so I couldn't >> > track it down. >> > >> > Anyway, please apply. >> > >> > >> > regards, >> > Ramana >> > >> > >> > Hi Ramana, > > Since I have no write access, would you mind to help to check in this patch? > The patch is attached. > > ChangeLog > 2013-01-31 Xinyu Qi <xyqi@marvell.com> > > * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment. > * config/arm/iwmmxt.md (WCGR0): Update. > (WCGR1, WCGR2, WCGR3): Likewise. > Now applied to trunk .sorry about the delay. Ramana
Hi, According to Vladimir Makarov's analysis, the root cause of PR target/54338 is that ALL_REGS doesn't contain IWMMXT_GR_REGS in REG_CLASS_CONTENTS. It seems there is no reason to exclude the IWMMXT_GR_REGS from ALL_REGS as IWMMXT_GR_REGS are the real registers. This patch simply makes ALL_REGS include IWMMXT_GR_REGS to fix this PR. Since the test case gcc.target/arm/mmx-2.c would fail for the same reason and become pass with this fix, no extra test case need to be add. Pass arm.exp test. Patch attached. ChangeLog 2013-04-02 Xinyu Qi <xyqi@marvell.com> * config/arm/arm.h (REG_CLASS_CONTENTS): Include IWMMXT_GR_REGS in ALL_REGS. OK? Thanks, Xinyu
On 04/02/13 10:40, Xinyu Qi wrote: > Hi, > According to Vladimir Makarov's analysis, the root cause of PR target/54338 is that ALL_REGS doesn't contain IWMMXT_GR_REGS in REG_CLASS_CONTENTS. > It seems there is no reason to exclude the IWMMXT_GR_REGS from ALL_REGS as IWMMXT_GR_REGS are the real registers. > This patch simply makes ALL_REGS include IWMMXT_GR_REGS to fix this PR. > Since the test case gcc.target/arm/mmx-2.c would fail for the same reason and become pass with this fix, no extra test case need to be add. > Pass arm.exp test. Patch attached. Testing just with arm.exp is not enough. Ok if no regressions running the entire regression testsuite for C and C++ for arm*-*-*eabi with an iwmmxt configuration. Thanks Ramana
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def index 3123426..f4dd6cc 100644 --- a/gcc/config/arm/arm-arches.def +++ b/gcc/config/arm/arm-arches.def @@ -57,4 +57,4 @@ ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M) ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM) ARM_ARCH("ep9312", ep9312, 4T, FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4) ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT) -ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT) +ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index d82b10b..c82eada 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -105,7 +105,7 @@ ARM_CORE("arm1020e", arm1020e, 5TE, FL_LDSCHED, fastmul) ARM_CORE("arm1022e", arm1022e, 5TE, FL_LDSCHED, fastmul) ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale) ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) -ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) +ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2, xscale) ARM_CORE("fa606te", fa606te, 5TE, FL_LDSCHED, 9e) ARM_CORE("fa626te", fa626te, 5TE, FL_LDSCHED, 9e) ARM_CORE("fmp626", fmp626, 5TE, FL_LDSCHED, 9e) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7a98197..b0680ab 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -685,6 +685,7 @@ static int thumb_call_reg_needed; #define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ +#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ /* Flags that only effect tuning, not available instructions. */ #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ @@ -766,6 +767,9 @@ int arm_arch_cirrus = 0; /* Nonzero if this chip supports Intel Wireless MMX technology. */ int arm_arch_iwmmxt = 0; +/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ +int arm_arch_iwmmxt2 = 0; + /* Nonzero if this chip is an XScale. */ int arm_arch_xscale = 0; @@ -1717,6 +1721,7 @@ arm_option_override (void) arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; + arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0; arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0; arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0; arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; @@ -1817,14 +1822,17 @@ arm_option_override (void) } /* FPA and iWMMXt are incompatible because the insn encodings overlap. - VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon - will ever exist. GCC makes no attempt to support this combination. */ - if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) - sorry ("iWMMXt and hardware floating point"); + VFP and iWMMXt however can coexist. */ + if (TARGET_IWMMXT && TARGET_HARD_FLOAT && !TARGET_VFP) + error ("iWMMXt and non-VFP floating point unit are incompatible"); + + /* iWMMXt and NEON are incompatible. */ + if (TARGET_IWMMXT && TARGET_NEON) + error ("iWMMXt and NEON are incompatible"); - /* ??? iWMMXt insn patterns need auditing for Thumb-2. */ - if (TARGET_THUMB2 && TARGET_IWMMXT) - sorry ("Thumb-2 iWMMXt"); + /* iWMMXt unsupported under Thumb mode. */ + if (TARGET_THUMB && TARGET_IWMMXT) + error ("iWMMXt unsupported under Thumb mode"); /* __fp16 support currently assumes the core has ldrh. */ if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE) @@ -20867,7 +20875,8 @@ arm_expand_binop_builtin (enum insn_code icode, || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); + gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode) + && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode)); if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f4204e4..c51bce9 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -97,6 +97,8 @@ extern char arm_arch_name[]; builtin_define ("__XSCALE__"); \ if (arm_arch_iwmmxt) \ builtin_define ("__IWMMXT__"); \ + if (arm_arch_iwmmxt2) \ + builtin_define ("__IWMMXT2__"); \ if (TARGET_AAPCS_BASED) \ { \ if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ @@ -194,7 +196,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK) #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) #define TARGET_IWMMXT (arm_arch_iwmmxt) +#define TARGET_IWMMXT2 (arm_arch_iwmmxt2) #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) +#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) #define TARGET_ARM (! TARGET_THUMB) #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ @@ -410,6 +414,9 @@ extern int arm_arch_cirrus; /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ extern int arm_arch_iwmmxt; +/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ +extern int arm_arch_iwmmxt2; + /* Nonzero if this chip is an XScale. */ extern int arm_arch_xscale; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index bbf6380..ad9d948 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -197,7 +197,7 @@ ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without ; arm_arch6. This attribute is used to compute attribute "enabled", ; use type "any" to enable an alternative in all cases. -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8" +(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8,iwmmxt,iwmmxt2" (const_string "any")) (define_attr "arch_enabled" "no,yes" @@ -248,6 +248,10 @@ (and (eq_attr "arch" "neon_nota8") (not (eq_attr "tune" "cortexa8")) (match_test "TARGET_NEON")) + (const_string "yes") + + (and (eq_attr "arch" "iwmmxt2") + (match_test "TARGET_REALLY_IWMMXT2")) (const_string "yes")] (const_string "no")))
From: Xinyu Qi <xyqi@marvell.com> gcc/ * config/arm/arm.c (FL_IWMMXT2): New define. (arm_arch_iwmmxt2): New variable. (arm_option_override): Enable use of iWMMXt with VFP. Disable use of iWMMXt with NEON. Disable use of iWMMXt under Thumb mode. Set arm_arch_iwmmxt2. (arm_expand_binop_builtin): Accept VOIDmode op. * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __IWMMXT2__. (TARGET_IWMMXT2): New define. (TARGET_REALLY_IWMMXT2): Likewise. (arm_arch_iwmmxt2): Declare. * config/arm/arm-cores.def (iwmmxt2): Add FL_IWMMXT2. * config/arm/arm-arches.def (iwmmxt2): Likewise. * config/arm/arm.md (arch): Add "iwmmxt2". (arch_enabled): Handle "iwmmxt2". --- gcc/config/arm/arm-arches.def | 2 +- gcc/config/arm/arm-cores.def | 2 +- gcc/config/arm/arm.c | 25 +++++++++++++++++-------- gcc/config/arm/arm.h | 7 +++++++ gcc/config/arm/arm.md | 6 +++++- 5 files changed, 31 insertions(+), 11 deletions(-)