From patchwork Fri Jan 14 16:08:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 78943 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 95415B70B3 for ; Sat, 15 Jan 2011 03:11:39 +1100 (EST) Received: (qmail 26843 invoked by alias); 14 Jan 2011 16:09:50 -0000 Received: (qmail 26388 invoked by uid 22791); 14 Jan 2011 16:09:37 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from b.mail.sonic.net (HELO b.mail.sonic.net) (64.142.19.5) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 14 Jan 2011 16:09:24 +0000 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by b.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p0EG9MJu028763 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 14 Jan 2011 08:09:22 -0800 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p0EG9MD9002083; Fri, 14 Jan 2011 08:09:22 -0800 Received: from anchor.twiddle.home (localhost.localdomain [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id p0EG9GiM028700; Fri, 14 Jan 2011 08:09:17 -0800 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id p0EG9E9T028699; Fri, 14 Jan 2011 08:09:14 -0800 From: rth@redhat.com To: gcc-patches@gcc.gnu.org Cc: nickc@redhat.com, Richard Henderson Subject: [PATCH 08/14] rx: Cleanup flags generation. Date: Fri, 14 Jan 2011 08:08:23 -0800 Message-Id: <1295021309-28608-9-git-send-email-rth@redhat.com> In-Reply-To: <1295021309-28608-1-git-send-email-rth@redhat.com> References: <1295021309-28608-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org From: Richard Henderson All arithmetic should only clobber the flags by default; setting the flags to a useful value should be done by a separate pattern. --- gcc/config/rx/rx-protos.h | 1 + gcc/config/rx/rx.c | 28 ++++ gcc/config/rx/rx.md | 306 +++++++++++++++++++++++++++++++++++---------- 3 files changed, 266 insertions(+), 69 deletions(-) diff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h index f0c2105..9bb76b2 100644 --- a/gcc/config/rx/rx-protos.h +++ b/gcc/config/rx/rx-protos.h @@ -42,6 +42,7 @@ extern void rx_notice_update_cc (rtx body, rtx insn); extern void rx_split_cbranch (Mmode, Rcode, rtx, rtx, rtx); extern bool rx_split_fp_compare (Rcode, Rcode *, Rcode *); extern Mmode rx_select_cc_mode (Rcode, rtx, rtx); +extern bool rx_match_ccmode (rtx, Mmode); #endif #endif /* GCC_RX_PROTOS_H */ diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index 71fcc8e..35ef862 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -2755,6 +2755,34 @@ rx_split_cbranch (enum machine_mode cc_mode, enum rtx_code cmp1, emit_jump_insn (x); } +/* A helper function for matching parallels that set the flags. */ + +bool +rx_match_ccmode (rtx insn, enum machine_mode cc_mode) +{ + rtx op1, flags; + enum machine_mode flags_mode; + + gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2); + + op1 = XVECEXP (PATTERN (insn), 0, 1); + gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE); + + flags = SET_DEST (op1); + flags_mode = GET_MODE (flags); + + if (GET_MODE (SET_SRC (op1)) != flags_mode) + return false; + if (GET_MODE_CLASS (flags_mode) != MODE_CC) + return false; + + /* Ensure that the mode of FLAGS is compatible with CC_MODE. */ + if (flags_from_mode (flags_mode) & ~flags_from_mode (cc_mode)) + return false; + + return true; +} + #undef TARGET_FUNCTION_VALUE #define TARGET_FUNCTION_VALUE rx_function_value diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md index cdae1cd..e2cc07a 100644 --- a/gcc/config/rx/rx.md +++ b/gcc/config/rx/rx.md @@ -915,9 +915,7 @@ (define_insn "abssi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (abs:SI (match_operand:SI 1 "register_operand" "0,r"))) - (set (reg:CC_ZSO CC_REG) - (compare:CC_ZSO (abs:SI (match_dup 1)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ abs\t%0 @@ -925,13 +923,24 @@ [(set_attr "length" "2,3")] ) +(define_insn "*abssi2_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (abs:SI (match_operand:SI 1 "register_operand" "0,r"))) + (set (reg CC_REG) + (compare (abs:SI (match_dup 1)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSOmode)" + "@ + abs\t%0 + abs\t%1, %0" + [(set_attr "length" "2,3")] +) + (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r") (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0") (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))) - (set (reg:CC_ZSC CC_REG) ;; See subsi3 - (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ add\t%2, %0 @@ -952,14 +961,39 @@ (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")] ) +(define_insn "*addsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r") + (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0") + (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))) + (set (reg CC_REG) + (compare (plus:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)" + "@ + add\t%2, %0 + add\t%2, %0 + sub\t%N2, %0 + add\t%2, %0 + add\t%2, %0 + add\t%2, %0 + add\t%2, %0 + add\t%1, %0 + add\t%2, %1, %0 + add\t%2, %1, %0 + add\t%2, %1, %0 + add\t%2, %1, %0 + add\t%2, %1, %0 + add\t%Q2, %0" + [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33") + (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")] +) + (define_insn "adddi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r") (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0,0") (match_operand:DI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))) - (set (reg:CC_ZSC CC_REG) ;; See subsi3 - (compare:CC_ZSC (plus:DI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "add\t%L2, %L0\n\tadc\t%H2, %H0" [(set_attr "timings" "22,22,22,22,22,44") @@ -970,9 +1004,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (and:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ and\t%2, %0 @@ -988,6 +1020,28 @@ (set_attr "length" "2,2,3,4,5,6,2,5,5")] ) +(define_insn "*andsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") + (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") + (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) + (set (reg CC_REG) + (compare (and:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "@ + and\t%2, %0 + and\t%2, %0 + and\t%2, %0 + and\t%2, %0 + and\t%2, %0 + and\t%2, %0 + and\t%1, %0 + and\t%2, %1, %0 + and\t%Q2, %0" + [(set_attr "timings" "11,11,11,11,11,11,11,33,33") + (set_attr "length" "2,2,3,4,5,6,2,5,5")] +) + ;; Byte swap (single 32-bit value). (define_insn "bswapsi2" [(set (match_operand:SI 0 "register_operand" "+r") @@ -1107,12 +1161,23 @@ (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (neg:SI (match_operand:SI 1 "register_operand" "0,r"))) - (set (reg:CC CC_REG) - (compare:CC (neg:SI (match_dup 1)) - (const_int 0)))] - ;; The NEG instruction does not comply with -fwrapv semantics. - ;; See gcc.c-torture/execute/pr22493-1.c for an example of this. - "! flag_wrapv" + (clobber (reg:CC CC_REG))] + "" + "@ + neg\t%0 + neg\t%1, %0" + [(set_attr "length" "2,3")] +) + +;; Note that the O and C flags are not set as per a normal compare, +;; and thus are unusable in that context. +(define_insn "*negsi2_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (neg:SI (match_operand:SI 1 "register_operand" "0,r"))) + (set (reg CC_REG) + (compare (neg:SI (match_dup 1)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" "@ neg\t%0 neg\t%1, %0" @@ -1122,9 +1187,7 @@ (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (not:SI (match_operand:SI 1 "register_operand" "0,r"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (not:SI (match_dup 1)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ not\t%0 @@ -1132,13 +1195,24 @@ [(set_attr "length" "2,3")] ) +(define_insn "*one_cmplsi2_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (not:SI (match_operand:SI 1 "register_operand" "0,r"))) + (set (reg CC_REG) + (compare (not:SI (match_dup 1)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "@ + not\t%0 + not\t%1, %0" + [(set_attr "length" "2,3")] +) + (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (ior:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ or\t%2, %0 @@ -1154,37 +1228,77 @@ (set_attr "length" "2,2,3,4,5,6,2,3,5")] ) +(define_insn "*iorsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") + (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") + (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) + (set (reg CC_REG) + (compare (ior:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "@ + or\t%2, %0 + or\t%2, %0 + or\t%2, %0 + or\t%2, %0 + or\t%2, %0 + or\t%Q2, %0 + or\t%1, %0 + or\t%2, %1, %0 + or\t%Q2, %0" + [(set_attr "timings" "11,11,11,11,11,11,11,11,33") + (set_attr "length" "2,2,3,4,5,6,2,3,5")] +) + (define_insn "rotlsi3" [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "rx_shift_operand" "rn"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (rotate:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "rotl\t%2, %0" [(set_attr "length" "3")] ) +(define_insn "*rotlsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotate:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "rx_shift_operand" "rn"))) + (set (reg CC_REG) + (compare (rotate:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "rotl\t%2, %0" + [(set_attr "length" "3")] +) + (define_insn "rotrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (rotatert:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "rx_shift_operand" "rn"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (rotatert:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "rotr\t%2, %0" [(set_attr "length" "3")] ) +(define_insn "*rotrsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotatert:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "rx_shift_operand" "rn"))) + (set (reg CC_REG) + (compare (rotatert:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "rotr\t%2, %0" + [(set_attr "length" "3")] +) + (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (ashiftrt:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ shar\t%2, %0 @@ -1193,13 +1307,26 @@ [(set_attr "length" "3,2,3")] ) +(define_insn "*ashrsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") + (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) + (set (reg CC_REG) + (compare (ashiftrt:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "@ + shar\t%2, %0 + shar\t%2, %0 + shar\t%2, %1, %0" + [(set_attr "length" "3,2,3")] +) + (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (lshiftrt:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ shlr\t%2, %0 @@ -1208,13 +1335,26 @@ [(set_attr "length" "3,2,3")] ) +(define_insn "*lshrsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") + (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) + (set (reg CC_REG) + (compare (lshiftrt:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "@ + shlr\t%2, %0 + shlr\t%2, %0 + shlr\t%2, %1, %0" + [(set_attr "length" "3,2,3")] +) + (define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r") (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (ashift:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ shll\t%2, %0 @@ -1223,16 +1363,26 @@ [(set_attr "length" "3,2,3")] ) +(define_insn "*ashlsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r") + (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) + (set (reg CC_REG) + (compare (ashift:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "@ + shll\t%2, %0 + shll\t%2, %0 + shll\t%2, %1, %0" + [(set_attr "length" "3,2,3")] +) + (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0") (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))) - (set (reg:CC_ZSC CC_REG) - ;; Note - we do not acknowledge that the SUB instruction sets the Overflow - ;; flag because its interpretation is different from comparing the result - ;; against zero. Compile and run gcc.c-torture/execute/cmpsi-1.c to see this. - (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "@ sub\t%2, %0 @@ -1244,13 +1394,31 @@ (set_attr "length" "2,2,6,3,5")] ) +;; Note that the O flag is set as if (compare op1 op2) not for +;; what is described here, (compare op0 0). +(define_insn "*subsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") + (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0") + (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))) + (set (reg CC_REG) + (compare (minus:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)" + "@ + sub\t%2, %0 + sub\t%2, %0 + add\t%N2, %0 + sub\t%2, %1, %0 + sub\t%Q2, %0" + [(set_attr "timings" "11,11,11,11,33") + (set_attr "length" "2,2,6,3,5")] +) + (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=r,r") (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "rx_source_operand" "r,Q"))) - (set (reg:CC_ZSC CC_REG) ;; See subsi3 - (compare:CC_ZSC (minus:DI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "sub\t%L2, %L0\n\tsbb\t%H2, %H0" [(set_attr "timings" "22,44") @@ -1262,14 +1430,26 @@ (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (xor:SI (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "" "xor\t%Q2, %0" [(set_attr "timings" "11,11,11,11,11,33") (set_attr "length" "3,4,5,6,7,6")] ) + +(define_insn "*xorsi3_flags" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") + (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") + (match_operand:SI 2 "rx_source_operand" + "r,Sint08,Sint16,Sint24,i,Q"))) + (set (reg CC_REG) + (compare (xor:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "xor\t%Q2, %0" + [(set_attr "timings" "11,11,11,11,11,33") + (set_attr "length" "3,4,5,6,7,6")] +) ;; Floating Point Instructions @@ -1277,9 +1457,7 @@ [(set (match_operand:SF 0 "register_operand" "=r,r,r") (plus:SF (match_operand:SF 1 "register_operand" "%0,0,0") (match_operand:SF 2 "rx_source_operand" "r,F,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (plus:SF (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "ALLOW_RX_FPU_INSNS" "fadd\t%2, %0" [(set_attr "timings" "44,44,66") @@ -1290,9 +1468,7 @@ [(set (match_operand:SF 0 "register_operand" "=r,r,r") (div:SF (match_operand:SF 1 "register_operand" "0,0,0") (match_operand:SF 2 "rx_source_operand" "r,F,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (div:SF (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "ALLOW_RX_FPU_INSNS" "fdiv\t%2, %0" [(set_attr "timings" "1616,1616,1818") @@ -1303,9 +1479,7 @@ [(set (match_operand:SF 0 "register_operand" "=r,r,r") (mult:SF (match_operand:SF 1 "register_operand" "%0,0,0") (match_operand:SF 2 "rx_source_operand" "r,F,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (mult:SF (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "ALLOW_RX_FPU_INSNS" "fmul\t%2, %0" [(set_attr "timings" "33,33,55") @@ -1316,9 +1490,7 @@ [(set (match_operand:SF 0 "register_operand" "=r,r,r") (minus:SF (match_operand:SF 1 "register_operand" "0,0,0") (match_operand:SF 2 "rx_source_operand" "r,F,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (minus:SF (match_dup 1) (match_dup 2)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "ALLOW_RX_FPU_INSNS" "fsub\t%Q2, %0" [(set_attr "timings" "44,44,66") @@ -1328,9 +1500,7 @@ (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (fix:SI (match_dup 1)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "ALLOW_RX_FPU_INSNS" "ftoi\t%Q1, %0" [(set_attr "timings" "22,44") @@ -1340,9 +1510,7 @@ (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=r,r") (float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q"))) - (set (reg:CC_ZS CC_REG) - (compare:CC_ZS (float:SF (match_dup 1)) - (const_int 0)))] + (clobber (reg:CC CC_REG))] "ALLOW_RX_FPU_INSNS" "itof\t%Q1, %0" [(set_attr "timings" "22,44")