From patchwork Mon Jan 10 20:31:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 78207 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 195EFB710C for ; Tue, 11 Jan 2011 07:34:13 +1100 (EST) Received: (qmail 19787 invoked by alias); 10 Jan 2011 20:32:42 -0000 Received: (qmail 19457 invoked by uid 22791); 10 Jan 2011 20:32:31 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (140.186.70.92) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 10 Jan 2011 20:32:22 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PcOPY-0006x2-MD for gcc-patches@gcc.gnu.org; Mon, 10 Jan 2011 15:32:20 -0500 Received: from b.mail.sonic.net ([64.142.19.5]:41302) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PcOPY-0006wm-Ak for gcc-patches@gcc.gnu.org; Mon, 10 Jan 2011 15:32:16 -0500 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by b.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p0AKWFse032154 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 Jan 2011 12:32:15 -0800 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p0AKWFhf006757; Mon, 10 Jan 2011 12:32:15 -0800 Received: from anchor.twiddle.home (localhost.localdomain [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id p0AKWCaM019672; Mon, 10 Jan 2011 12:32:13 -0800 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id p0AKWB23019671; Mon, 10 Jan 2011 12:32:11 -0800 From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: nickc@redhat.com, law@redhat.com, Richard Henderson Subject: [PATCH 06/28] mn10300: fp insn cleanup Date: Mon, 10 Jan 2011 12:31:35 -0800 Message-Id: <1294691517-19580-7-git-send-email-rth@redhat.com> In-Reply-To: <1294691517-19580-1-git-send-email-rth@redhat.com> References: <1294691517-19580-1-git-send-email-rth@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org From: Richard Henderson Delete integer-mode abssf2, negsf2; these will be handled by the middle-end now. Delete unnecessary expanders. --- gcc/config/mn10300/mn10300.md | 212 ++++------------------------------------ 1 files changed, 22 insertions(+), 190 deletions(-) diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md index 3fad021..3a266960 100644 --- a/gcc/config/mn10300/mn10300.md +++ b/gcc/config/mn10300/mn10300.md @@ -2577,74 +2577,8 @@ ;; ---------------------------------------------------------------------- ;; FP INSTRUCTIONS ;; ---------------------------------------------------------------------- -;; -;; The mn103 series does not have floating point instructions, but since -;; FP values are held in integer regs, we can clear the high bit easily -;; which gives us an efficient inline floating point absolute value. -;; -;; Similarly for negation of a FP value. -;; - -(define_expand "absdf2" - [(set (match_operand:DF 0 "register_operand") - (abs:DF (match_operand:DF 1 "register_operand")))] - "" - " -{ - rtx target, result, insns; - - start_sequence (); - target = operand_subword (operands[0], 1, 1, DFmode); - result = expand_binop (SImode, and_optab, - operand_subword_force (operands[1], 1, DFmode), - GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN); - - gcc_assert (result); - - if (result != target) - emit_move_insn (result, target); - - emit_move_insn (operand_subword (operands[0], 0, 1, DFmode), - operand_subword_force (operands[1], 0, DFmode)); - - insns = get_insns (); - end_sequence (); - - emit_insn (insns); - DONE; -}") - -(define_expand "abssf2" - [(set (match_operand:SF 0 "register_operand") - (abs:SF (match_operand:SF 1 "register_operand")))] - "" - " -{ - rtx result; - rtx target; - - if (TARGET_AM33_2) - { - emit_insn (gen_abssf2_am33_2 (operands[0], operands[1])); - DONE; - } - - target = operand_subword_force (operands[0], 0, SFmode); - result = expand_binop (SImode, and_optab, - operand_subword_force (operands[1], 0, SFmode), - GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN); - gcc_assert (result); - if (result != target) - emit_move_insn (result, target); - - /* Make a place for REG_EQUAL. */ - emit_move_insn (operands[0], operands[0]); - DONE; -}") - - -(define_insn "abssf2_am33_2" +(define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=f,f") (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))] "TARGET_AM33_2" @@ -2655,67 +2589,7 @@ (const_int 17) (const_int 14)))] ) -(define_expand "negdf2" - [(set (match_operand:DF 0 "register_operand") - (neg:DF (match_operand:DF 1 "register_operand")))] - "" - " -{ - rtx target, result, insns; - - start_sequence (); - target = operand_subword (operands[0], 1, 1, DFmode); - result = expand_binop (SImode, xor_optab, - operand_subword_force (operands[1], 1, DFmode), - GEN_INT (trunc_int_for_mode (0x80000000, SImode)), - target, 0, OPTAB_WIDEN); - - gcc_assert (result); - - if (result != target) - emit_move_insn (result, target); - - emit_move_insn (operand_subword (operands[0], 0, 1, DFmode), - operand_subword_force (operands[1], 0, DFmode)); - - insns = get_insns (); - end_sequence (); - - emit_insn (insns); - DONE; -}") - -(define_expand "negsf2" - [(set (match_operand:SF 0 "register_operand") - (neg:SF (match_operand:SF 1 "register_operand")))] - "" - " -{ - rtx result; - rtx target; - - if (TARGET_AM33_2) - { - emit_insn (gen_negsf2_am33_2 (operands[0], operands[1])); - DONE; - } - - target = operand_subword_force (operands[0], 0, SFmode); - result = expand_binop (SImode, xor_optab, - operand_subword_force (operands[1], 0, SFmode), - GEN_INT (trunc_int_for_mode (0x80000000, SImode)), - target, 0, OPTAB_WIDEN); - gcc_assert (result); - - if (result != target) - emit_move_insn (result, target); - - /* Make a place for REG_EQUAL. */ - emit_move_insn (operands[0], operands[0]); - DONE; -}") - -(define_insn "negsf2_am33_2" +(define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=f,f") (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))] "TARGET_AM33_2" @@ -2727,27 +2601,22 @@ ) (define_expand "sqrtsf2" - [(parallel [(set (match_operand:SF 0 "register_operand" "") - (sqrt:SF (match_operand:SF 1 "register_operand" ""))) - (clobber (reg:CC_FLOAT CC_REG)) - ]) - ] + [(set (match_operand:SF 0 "register_operand" "") + (sqrt:SF (match_operand:SF 1 "register_operand" "")))] "TARGET_AM33_2 && flag_unsafe_math_optimizations" - " - { - rtx scratch = gen_reg_rtx (SFmode); - emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode))); - emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)), - scratch)); - DONE; - }") +{ + rtx scratch = gen_reg_rtx (SFmode); + emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode))); + emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)), + scratch)); + DONE; +}) (define_insn "rsqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f,f") (div:SF (match_operand:SF 2 "const_1f_operand" "F,F") (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f")))) - (clobber (reg:CC_FLOAT CC_REG)) - ] + (clobber (reg:CC_FLOAT CC_REG))] "TARGET_AM33_2" "@ frsqrt %0 @@ -2756,22 +2625,11 @@ (const_int 4753) (const_int 2327)))] ) -(define_expand "addsf3" - [(parallel [(set (match_operand:SF 0 "register_operand") - (plus:SF (match_operand:SF 1 "register_operand") - (match_operand:SF 2 "nonmemory_operand"))) - (clobber (reg:CC_FLOAT CC_REG))]) - ] - "TARGET_AM33_2" - "" -) - -(define_insn "*addsf3_internal" +(define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=f,f") (plus:SF (match_operand:SF 1 "register_operand" "%0,f") (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) - (clobber (reg:CC_FLOAT CC_REG)) - ] + (clobber (reg:CC_FLOAT CC_REG))] "TARGET_AM33_2" "@ fadd %2, %0 @@ -2781,26 +2639,14 @@ (const_int 17) (const_int 14)) (if_then_else (eq_attr "cpu" "am34") (const_int 17) (const_int 25)) - ]) - ] -) - -(define_expand "subsf3" - [(parallel [(set (match_operand:SF 0 "register_operand") - (minus:SF (match_operand:SF 1 "register_operand") - (match_operand:SF 2 "nonmemory_operand"))) - (clobber (reg:CC_FLOAT CC_REG))]) - ] - "TARGET_AM33_2" - "" + ])] ) -(define_insn "*subsf3_internal" +(define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=f,f") (minus:SF (match_operand:SF 1 "register_operand" "0,f") (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) - (clobber (reg:CC_FLOAT CC_REG)) - ] + (clobber (reg:CC_FLOAT CC_REG))] "TARGET_AM33_2" "@ fsub %2, %0 @@ -2810,21 +2656,10 @@ (const_int 17) (const_int 14)) (if_then_else (eq_attr "cpu" "am34") (const_int 17) (const_int 25)) - ]) - ] + ])] ) -(define_expand "mulsf3" - [(parallel [(set (match_operand:SF 0 "register_operand") - (mult:SF (match_operand:SF 1 "register_operand") - (match_operand:SF 2 "nonmemory_operand"))) - (clobber (reg:CC_FLOAT CC_REG))]) - ] - "TARGET_AM33_2" - "" -) - -(define_insn "*mulsf3_internal" +(define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=f,f") (mult:SF (match_operand:SF 1 "register_operand" "%0,f") (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) @@ -2839,16 +2674,14 @@ (const_int 17) (const_int 14)) (if_then_else (eq_attr "cpu" "am34") (const_int 17) (const_int 25)) - ]) - ] + ])] ) (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=f,f") (div:SF (match_operand:SF 1 "register_operand" "0,f") (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) - (clobber (reg:CC_FLOAT CC_REG)) - ] + (clobber (reg:CC_FLOAT CC_REG))] "TARGET_AM33_2" "@ fdiv %2, %0 @@ -2858,8 +2691,7 @@ (const_int 2531) (const_int 1216)) (if_then_else (eq_attr "cpu" "am34") (const_int 2531) (const_int 1317)) - ]) - ] + ])] ) (define_insn "fmasf4"