From patchwork Wed Nov 19 15:05:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bennett X-Patchwork-Id: 412430 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8883414010F for ; Thu, 20 Nov 2014 02:05:41 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:content-transfer-encoding:mime-version; q=dns; s= default; b=hd/vJiD5VaRE0iUvBpVENEzj5mHjNfS20dX9q2WkPNHgkrOjsBIa1 UIO+2VXQlL7VE5CIZY0bH+jY6WFAfYpS3UQ9n2YJUpanauehk7Z9/e34PimKREW1 f0kp7fyq8UaKPkprNecvYwJpnhco4nmG5xG326bQ0jaNeOJ2RlHh6o= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:content-transfer-encoding:mime-version; s=default; bh=Pb9kyMjpSt6klLTbjeTS66/PHNo=; b=RyoFebeNTyR39nM6P089m1VdCYy5 AiAmWks2YV5V9j/foWRchyiaXF96FV7262ZhOqlcpT5ky5bEEg7MwKISnke9omOD WTV3sKjJzC8ngTBgFm/Vo10CWoHrlKT3s4LnElvGVMGP0R3f0EZALINnvXgb39sI DaEEOIXCy1t3/2s= Received: (qmail 3407 invoked by alias); 19 Nov 2014 15:05:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3396 invoked by uid 89); 19 Nov 2014 15:05:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 19 Nov 2014 15:05:31 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id BC6253AE32021; Wed, 19 Nov 2014 15:05:25 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 19 Nov 2014 15:05:28 +0000 Received: from LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9]) by LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9%17]) with mapi id 14.03.0210.002; Wed, 19 Nov 2014 15:05:27 +0000 From: Andrew Bennett To: Matthew Fortune , "Moore, Catherine" , "gcc-patches@gcc.gnu.org" CC: "Rozycki, Maciej" Subject: RE: [PATCH] If using branch likelies in MIPS sync code fill the delay slot with a nop Date: Wed, 19 Nov 2014 15:05:27 +0000 Message-ID: <0DA23CC379F5F945ACB41CF394B9827720F3431A@LEMAIL01.le.imgtec.org> References: <0DA23CC379F5F945ACB41CF394B9827720F331A8@LEMAIL01.le.imgtec.org> <6D39441BF12EF246A7ABCE6654B0235320F73768@LEMAIL01.le.imgtec.org> <0DA23CC379F5F945ACB41CF394B9827720F341BF@LEMAIL01.le.imgtec.org> <6D39441BF12EF246A7ABCE6654B0235320F75FAF@LEMAIL01.le.imgtec.org> In-Reply-To: <6D39441BF12EF246A7ABCE6654B0235320F75FAF@LEMAIL01.le.imgtec.org> MIME-Version: 1.0 X-IsSubscribed: yes > Please rephrase the comment along the lines of my previous suggestion. > This wording is too complex IMO. The patch containing the updated comment (which also keeps within 72 columns) is below. Ok to commit? Regards, Andrew diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 02268f3..bf5682c 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -12997,7 +12997,14 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands) This will sometimes be a delayed branch; see the write code below for details. */ mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); - mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL); + + /* When using branch likely (-mfix-r10000), the delay slot instruction + will be annulled on false. The normal delay slot instructions + calculate the overall result of the atomic operation and must not + be annulled. To ensure this behaviour unconditionally use a NOP + in the delay slot for the branch likely case. */ + + mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at, NULL); /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) @@ -13005,7 +13012,7 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands) mips_multi_copy_insn (tmp3_insn); mips_multi_set_operand (mips_multi_last_index (), 0, newval); } - else if (!(required_oldval && cmp)) + else if (!(required_oldval && cmp) && !mips_branch_likely) mips_multi_add_insn ("nop", NULL); /* CMP = 1 -- either standalone or in a delay slot. */ @@ -13029,12 +13036,12 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands) const char * mips_output_sync_loop (rtx_insn *insn, rtx *operands) { - mips_process_sync_loop (insn, operands); - /* Use branch-likely instructions to work around the LL/SC R10000 errata. */ mips_branch_likely = TARGET_FIX_R10000; + mips_process_sync_loop (insn, operands); + mips_push_asm_switch (&mips_noreorder); mips_push_asm_switch (&mips_nomacro); mips_push_asm_switch (&mips_noat); @@ -13056,6 +13063,9 @@ mips_output_sync_loop (rtx_insn *insn, rtx *operands) unsigned int mips_sync_loop_insns (rtx_insn *insn, rtx *operands) { + /* Use branch-likely instructions to work around the LL/SC R10000 + errata. */ + mips_branch_likely = TARGET_FIX_R10000; mips_process_sync_loop (insn, operands); return mips_multi_num_insns; }