From patchwork Fri Jun 9 12:53:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw (lists)" X-Patchwork-Id: 773890 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wkj7r6r1qz9s74 for ; Fri, 9 Jun 2017 23:00:24 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="PSguLuUF"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; q=dns; s= default; b=vr7x3mU45VXWIS/e63D3xsuw8vNv1xrxh7fwVPGWF8NBIGCk2PBPq dmqC7ww4gb5L7WpTP2jmP9RotLvJQgMExhCgmy+u2IY14Uktp+gRFVZNql73ydy8 CG/zS+gNS5CodIOkPeHfT5Fco9sNlU1ytQdiU+ncTAO3Wuroi2nDqg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; s=default; bh=KxP86couE1wWKGMuDXQ65xDAT0E=; b=PSguLuUFgjTmB0HAHwNWS8g12h4f iO73EsfEVksaCjqFu5XkJAz9c7kkLhKc15fDkpwfQ4ByWmd8nUrX0XN7KZBA2rAE reV1Ld1JSc8TmvzJzRUJZGA5mbqf7Vl/4YIS6pEbgQfUKA2H5L7XK+wrzKLCqkZB PWJXCLWzAw/Qrd0= Received: (qmail 97480 invoked by alias); 9 Jun 2017 12:54:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 86295 invoked by uid 89); 9 Jun 2017 12:54:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Jun 2017 12:54:35 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJJQs-0007jR-DT for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:31 -0400 Received: from foss.arm.com ([217.140.101.70]:47128) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJJQs-0007Te-3v for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:30 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CAD032B; Fri, 9 Jun 2017 05:54:29 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 58AE53F3E1; Fri, 9 Jun 2017 05:54:29 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 28/30] [arm] Add a few missing architecture extension options. Date: Fri, 9 Jun 2017 13:53:57 +0100 Message-Id: <01975565dd108d24c024c0e0fe042e3682b3ba95.1497004220.git.Richard.Earnshaw@arm.com> In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Reviewing the list of options for the purposes of writing the documentation revealed that a small number of options were missing. Mostly these are aliases for existing options, but in a couple of cases we lacked the ability to disable certain other options. * config/arm/arm-cpus.in (armv7): Add extension +nofp. (armv7-r): Add aliases vfpv3xd and vfpv3-d16. (armv8-m.main): Add option +nodsp. * config/arm/arm-cpu-cdata.h: Regenerated. --- gcc/config/arm/arm-cpu-cdata.h | 24 ++++++++++++++++++++++++ gcc/config/arm/arm-cpus.in | 6 ++++++ 2 files changed, 30 insertions(+) diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index ddfb05c..6cc2ea2 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -1856,6 +1856,10 @@ static const struct cpu_arch_extension arch_opttab_armv7[] = { { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } + }, + { "vfpv3-d16", false, true, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, @@ -2003,6 +2007,14 @@ static const struct cpu_arch_extension arch_opttab_armv7_r[] = { "noidiv", true, false, { isa_bit_adiv, isa_nobit } }, + { + "vfpv3xd", false, true, + { ISA_VFPv3, isa_nobit } + }, + { + "vfpv3-d16", false, true, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, { NULL, false, false, {isa_nobit}} }; @@ -2023,6 +2035,14 @@ static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, + { + "vfpv4-sp-d16", false, true, + { ISA_VFPv4, isa_nobit } + }, + { + "fpv5-d16", false, true, + { ISA_FPv5,ISA_FP_DBL, isa_nobit } + }, { NULL, false, false, {isa_nobit}} }; @@ -2111,6 +2131,10 @@ static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, + { + "nodsp", true, false, + { isa_bit_ARMv7em, isa_nobit } + }, { NULL, false, false, {isa_nobit}} }; diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 739de45..b0c0eae 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -228,6 +228,7 @@ begin arch armv7 # fp => VFPv3-d16 (only useful for the A+R profile subset). option fp add VFPv3 FP_DBL optalias vfpv3-d16 fp + option nofp remove ALL_FP end arch armv7 begin arch armv7-a @@ -281,7 +282,9 @@ begin arch armv7-r isa ARMv7r # ARMv7-r uses VFPv3-d16 option fp.sp add VFPv3 + optalias vfpv3xd fp.sp option fp add VFPv3 FP_DBL + optalias vfpv3-d16 fp option idiv add bit_adiv option nofp remove ALL_FP option noidiv remove bit_adiv @@ -303,8 +306,10 @@ begin arch armv7e-m isa ARMv7em # fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16 option fp add VFPv4 + optalias vfpv4-sp-d16 fp option fpv5 add FPv5 option fp.dp add FPv5 FP_DBL + optalias fpv5-d16 fp.dp option nofp remove ALL_FP end arch armv7e-m @@ -359,6 +364,7 @@ begin arch armv8-m.main option fp add FPv5 option fp.dp add FPv5 FP_DBL option nofp remove ALL_FP + option nodsp remove bit_ARMv7em end arch armv8-m.main begin arch iwmmxt