diff mbox series

[MIPS,committed] Fix wrong use of XINT instead of INTVAL

Message ID 00b401d3b151$c5da9420$518fbc60$@gmail.com
State New
Headers show
Series [MIPS,committed] Fix wrong use of XINT instead of INTVAL | expand

Commit Message

Matthew Fortune March 1, 2018, 11:38 a.m. UTC
Hi,

This issue was caught with assert checking enabled but is not a
functional bug as XINT(x, 0) happens to overlay INTVAL(x) anyway.

Committed to trunk.

Thanks,
Matthew

gcc/
	* config/mips/mips.c (mips_final_prescan_insn): Fix incorrect
	XINT with INTVAL.
	(mips_final_postscan_insn): Likewise.
---
 gcc/config/mips/mips.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

   if (mips_need_noat_wrapper_p (insn, opvec, noperands))
@@ -20450,7 +20450,7 @@ mips_final_postscan_insn (FILE *file
ATTRIBUTE_UNUSED, rtx_insn *insn,
       && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
       && XINT (PATTERN (insn), 1) == UNSPEC_CONSTTABLE_END)
     mips_set_text_contents_type (asm_out_file, "__pend_",
-				 XINT (XVECEXP (PATTERN (insn), 0, 0), 0),
+				 INTVAL (XVECEXP (PATTERN (insn), 0, 0)),
 				 TRUE);
 }

Comments

Maciej W. Rozycki March 1, 2018, 12:39 p.m. UTC | #1
Hi Matthew,

> This issue was caught with assert checking enabled but is not a
> functional bug as XINT(x, 0) happens to overlay INTVAL(x) anyway.

 There's an intriguing difference between XINT (x, 0) and XWINT (x, 0) 
involved here though, which does not appear to be documented in the 
manual, and certainly not in Section 13.3 "Access to Operands" where I'd 
expect it.  I gather it is a matter of the operand being treated as `int' 
vs HOST_WIDE_INT, and that is where the assertion comes from, as these 
data types will necessarily be different for most hosts and cause an issue 
here right away if the host is big-endian.

 Thanks for catching and fixing this!

  Maciej
diff mbox series

Patch

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 00cece2..aabd4b1 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -20426,7 +20426,7 @@  mips_final_prescan_insn (rtx_insn *insn, rtx *opvec,
int noperands)
       && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
       && XINT (PATTERN (insn), 1) == UNSPEC_CONSTTABLE)
     mips_set_text_contents_type (asm_out_file, "__pool_",
-				 XINT (XVECEXP (PATTERN (insn), 0, 0), 0),
+				 INTVAL (XVECEXP (PATTERN (insn), 0, 0)),
 				 FALSE);