| Message ID | 004801d02fe2$ebebfc10$c3c3f430$@arm.com |
|---|---|
| State | New |
| Headers | show |
On 14/01/15 10:14, Hale Wang wrote: > Hi, > > This patch is tuned particularly for benchmark performance on cortex-m7. > Tested with GCC regression test, no regressions. Is it ok for trunk? > > BR, > Hale Wang > > gcc/ChangeLog > 2014-12-24 Hale Wang <hale.wang@arm.com> > > * config/arm/arm.c: Tune the max_cond_insns/branch_cost for > Cortex-M7. > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 8193bf1..d52fcbd 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -287,6 +287,7 @@ static unsigned int arm_autovectorize_vector_sizes > (void); > static int arm_default_branch_cost (bool, bool); > static int arm_cortex_a5_branch_cost (bool, bool); > static int arm_cortex_m_branch_cost (bool, bool); > +static int arm_cortex_m7_branch_cost (bool, bool); > > static bool arm_vectorize_vec_perm_const_ok (machine_mode vmode, > const unsigned char *sel); > @@ -1967,10 +1968,10 @@ const struct tune_params arm_cortex_m7_tune = > &v7m_extra_costs, > NULL, /* Sched adj cost. > */ > 0, /* Constant limit. */ > - 0, /* Max cond insns. */ > + 1, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > true, /* Prefer constant > pool. */ > - arm_cortex_m_branch_cost, > + arm_cortex_m7_branch_cost, > false, /* Prefer LDRD/STRD. */ > {true, true}, /* Prefer non short > circuit. */ > &arm_default_vec_cost, /* Vectorizer costs. */ > @@ -12015,6 +12016,12 @@ arm_cortex_m_branch_cost (bool speed_p, bool > predictable_p) > : arm_default_branch_cost (speed_p, predictable_p); > } > > +static int > +arm_cortex_m7_branch_cost (bool speed_p, bool predictable_p) > +{ > + return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p); > +} > + > static bool fp_consts_inited = false; > > static REAL_VALUE_TYPE value_fp0; > OK. Ramana
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 8193bf1..d52fcbd 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -287,6 +287,7 @@ static unsigned int arm_autovectorize_vector_sizes (void); static int arm_default_branch_cost (bool, bool); static int arm_cortex_a5_branch_cost (bool, bool); static int arm_cortex_m_branch_cost (bool, bool); +static int arm_cortex_m7_branch_cost (bool, bool); static bool arm_vectorize_vec_perm_const_ok (machine_mode vmode,
Hi, This patch is tuned particularly for benchmark performance on cortex-m7. Tested with GCC regression test, no regressions. Is it ok for trunk? BR, Hale Wang gcc/ChangeLog 2014-12-24 Hale Wang <hale.wang@arm.com> * config/arm/arm.c: Tune the max_cond_insns/branch_cost for Cortex-M7. const unsigned char *sel); @@ -1967,10 +1968,10 @@ const struct tune_params arm_cortex_m7_tune = &v7m_extra_costs, NULL, /* Sched adj cost. */ 0, /* Constant limit. */ - 0, /* Max cond insns. */ + 1, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ - arm_cortex_m_branch_cost, + arm_cortex_m7_branch_cost, false, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -12015,6 +12016,12 @@ arm_cortex_m_branch_cost (bool speed_p, bool predictable_p) : arm_default_branch_cost (speed_p, predictable_p); } +static int +arm_cortex_m7_branch_cost (bool speed_p, bool predictable_p) +{ + return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p); +} + static bool fp_consts_inited = false; static REAL_VALUE_TYPE value_fp0;