From patchwork Thu Jul 10 08:06:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Terry Guo X-Patchwork-Id: 368499 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D5456140141 for ; Thu, 10 Jul 2014 18:06:30 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=UHL8qGOOvLQLqwp7x+tfFK7I70W7KsbriiP0UeSPjM6lKAA9qj DessvgsVqZe3EL0CYch1AxgKzaWOQqKEalqiagRIQcVUJMHdETedAMH6/393Orli 3jmsEYtyh/aWbBNG0vTQbPOsORuji2olbSaleAohF/JQcHDOEqDpxB7zg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=7UAvRb9PJermlVxGiRkYRKQlrRQ=; b=lUYUKGiz91cKGfWOAyBS 7njtwbyjhF3GO9qWTAYCnuwDqMAeJEjORwFZccIIOhZYDcb8TdDI8zwpRwq5S3wS WdU9FOUeQQrQqJ9iFX8dgqPvGpEC5Kwvaov2JJk5xxMPDgMiQAhClP0uPDevUUCR /u3QJ3lujGDKRF/9REl6qPY= Received: (qmail 5485 invoked by alias); 10 Jul 2014 08:06:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5472 invoked by uid 89); 10 Jul 2014 08:06:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 10 Jul 2014 08:06:20 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 10 Jul 2014 09:06:17 +0100 Received: from shawin252 ([10.164.2.180]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 10 Jul 2014 09:06:14 +0100 From: "Terry Guo" To: Cc: "Marcus Shawcroft" , "Ramana Radhakrishnan" Subject: [Patch 2/2][AArch64]Split insn type alu_reg into alu_sreg and alu_dsp_reg Date: Thu, 10 Jul 2014 16:06:11 +0800 Message-ID: <004101cf9c15$d1dd9600$7598c200$@arm.com> MIME-Version: 1.0 X-MC-Unique: 114071009061700701 X-IsSubscribed: yes Hi there, As the second and final patch in this series, it intends to update alu_reg and alus_reg types for AArch64 port. With this change, the gcc can be successfully built for AArch64. Is it OK to trunk? BR, Terry 2014-07-10 Terry Guo * config/aarch64/aarch64.md (*addsi3_aarch64, *addsi3_aarch64_uxtw, subsi3, *adddi3_aarch64, *subsi3_uxtw, subdi3, absdi2, neg2, add_losym_, *negsi2_uxtw, tlsle_small_): Rename type alu_reg to alu_sreg. (add3_compare0, *addsi3_compare0_uxtw, *add3nr_compare0, sub3_compare0, *compare_neg, *neg2_compare0, subsi3_compare0_uxtw, *negsi2_compare0_uxtw, *cmp): Rename type alus_reg to alus_sreg. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3eb783c..76d8cd3 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1167,7 +1167,7 @@ add\\t%w0, %w1, %w2 add\\t%0.2s, %1.2s, %2.2s sub\\t%w0, %w1, #%n2" - [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm") + [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm") (set_attr "simd" "*,*,yes,*")] ) @@ -1183,7 +1183,7 @@ add\\t%w0, %w1, %2 add\\t%w0, %w1, %w2 sub\\t%w0, %w1, #%n2" - [(set_attr "type" "alu_imm,alu_reg,alu_imm")] + [(set_attr "type" "alu_imm,alu_sreg,alu_imm")] ) (define_insn "*adddi3_aarch64" @@ -1198,7 +1198,7 @@ add\\t%x0, %x1, %x2 sub\\t%x0, %x1, #%n2 add\\t%d0, %d1, %d2" - [(set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg") + [(set_attr "type" "alu_imm,alu_sreg,alu_imm,alu_sreg") (set_attr "simd" "*,*,*,yes")] ) @@ -1234,7 +1234,7 @@ adds\\t%0, %1, %2 adds\\t%0, %1, %2 subs\\t%0, %1, #%n2" - [(set_attr "type" "alus_reg,alus_imm,alus_imm")] + [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) ;; zero_extend version of above @@ -1251,7 +1251,7 @@ adds\\t%w0, %w1, %w2 adds\\t%w0, %w1, %w2 subs\\t%w0, %w1, #%n2" - [(set_attr "type" "alus_reg,alus_imm,alus_imm")] + [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) (define_insn "*adds_mul_imm_" @@ -1365,7 +1365,7 @@ cmn\\t%0, %1 cmn\\t%0, %1 cmp\\t%0, #%n1" - [(set_attr "type" "alus_reg,alus_imm,alus_imm")] + [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) (define_insn "*compare_neg" @@ -1375,7 +1375,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "cmn\\t%1, %0" - [(set_attr "type" "alus_reg")] + [(set_attr "type" "alus_sreg")] ) (define_insn "*add__" @@ -1647,7 +1647,7 @@ (match_operand:SI 2 "register_operand" "r")))] "" "sub\\t%w0, %w1, %w2" - [(set_attr "type" "alu_reg")] + [(set_attr "type" "alu_sreg")] ) ;; zero_extend version of above @@ -1658,7 +1658,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "sub\\t%w0, %w1, %w2" - [(set_attr "type" "alu_reg")] + [(set_attr "type" "alu_sreg")] ) (define_insn "subdi3" @@ -1669,7 +1669,7 @@ "@ sub\\t%x0, %x1, %x2 sub\\t%d0, %d1, %d2" - [(set_attr "type" "alu_reg, neon_sub") + [(set_attr "type" "alu_sreg, neon_sub") (set_attr "simd" "*,yes")] ) @@ -1701,7 +1701,7 @@ (minus:GPI (match_dup 1) (match_dup 2)))] "" "subs\\t%0, %1, %2" - [(set_attr "type" "alus_reg")] + [(set_attr "type" "alus_sreg")] ) ;; zero_extend version of above @@ -1714,7 +1714,7 @@ (zero_extend:DI (minus:SI (match_dup 1) (match_dup 2))))] "" "subs\\t%w0, %w1, %w2" - [(set_attr "type" "alus_reg")] + [(set_attr "type" "alus_sreg")] ) (define_insn "*sub__" @@ -1925,7 +1925,7 @@ GEN_INT (63))))); DONE; } - [(set_attr "type" "alu_reg")] + [(set_attr "type" "alu_sreg")] ) (define_insn "neg2" @@ -1935,7 +1935,7 @@ "@ neg\\t%0, %1 neg\\t%0, %1" - [(set_attr "type" "alu_reg, neon_neg") + [(set_attr "type" "alu_sreg, neon_neg") (set_attr "simd" "*,yes")] ) @@ -1945,7 +1945,7 @@ (zero_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))] "" "neg\\t%w0, %w1" - [(set_attr "type" "alu_reg")] + [(set_attr "type" "alu_sreg")] ) (define_insn "*ngc" @@ -1975,7 +1975,7 @@ (neg:GPI (match_dup 1)))] "" "negs\\t%0, %1" - [(set_attr "type" "alus_reg")] + [(set_attr "type" "alus_sreg")] ) ;; zero_extend version of above @@ -1987,7 +1987,7 @@ (zero_extend:DI (neg:SI (match_dup 1))))] "" "negs\\t%w0, %w1" - [(set_attr "type" "alus_reg")] + [(set_attr "type" "alus_sreg")] ) (define_insn "*neg_3_compare0" @@ -2266,7 +2266,7 @@ cmp\\t%0, %1 cmp\\t%0, %1 cmn\\t%0, #%n1" - [(set_attr "type" "alus_reg,alus_imm,alus_imm")] + [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) (define_insn "*cmp" @@ -3790,7 +3790,7 @@ (match_operand 2 "aarch64_valid_symref" "S")))] "" "add\\t%0, %1, :lo12:%a2" - [(set_attr "type" "alu_reg")] + [(set_attr "type" "alu_sreg")] ) (define_insn "ldr_got_small_" @@ -3901,7 +3901,7 @@ UNSPEC_GOTSMALLTLS))] "" "add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2" - [(set_attr "type" "alu_reg") + [(set_attr "type" "alu_sreg") (set_attr "length" "8")] )