diff mbox

[combine] PR46164: Don't combine the insns if a volatile register is contained.

Message ID 003d01d03971$89872ed0$9c958c70$@arm.com
State New
Headers show

Commit Message

Hale Wang Jan. 26, 2015, 2:08 p.m. UTC 
> -----Original Message-----
> From: Andrew Pinski [mailto:pinskia@gmail.com]
> Sent: Monday, January 26, 2015 6:03 PM
> To: Hale Wang
> Cc: GCC Patches
> Subject: Re: [PATCH] [gcc, combine] PR46164: Don't combine the insns if a
> volatile register is contained.
> 
> 
> I think it is allowed to the second combining, just not the first.
> Also it is not about volatile registers here but rather user specified registers
> into inline-asm.
> Also I thought can_combine_p would reject combing into an inline-asm to
> prevent this issue.
> 

Hi Andrew,

Thanks a lot.
As you suggested, I changed the patch to reject combing into an inline-asm. I have attached the patch.
Is it OK for you?

BR,
Hale

> Thanks,
> Andrew
> 
> >
> > This patch is used to disable the combine operation if the insns
> > contain volatile registers. A new test case is also added in this patch.
> >
> > Is it OK for trunk?
> >
> > BR,
> > Hale Wang
> >
> > ChangeLog:
> >
> > 2015-01-22  Hale Wang  <hale.wang@arm.com>
> >
> >         PR middle-end/46164
> >         * combine.c (can_combine_p): Don't combine the insns if
> >         a volatile register is contained.
> >
> > 2015-01-22  Hale Wang  <hale.wang@arm.com>
> >
> >         PR middle-end/46164
> >         * gcc.target/arm/pr46164.c: New test.
diff mbox

Patch

diff --git a/gcc/combine.c b/gcc/combine.c
index 5c763b4..2e8290a 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1769,7 +1769,7 @@  can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
 {
   int i;
   const_rtx set = 0;
-  rtx src, dest;
+  rtx src, dest, asm_op;
   rtx_insn *p;
 #ifdef AUTO_INC_DEC
   rtx link;
@@ -1983,6 +1983,10 @@  can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
   else if (GET_CODE (dest) != CC0)
     return 0;
 
+  /* If i3 contains an inline-asm operand, reject, because the user specified
+     registers in the inline-asm maybe removed by the combining.  */
+  if ((asm_op = extract_asm_operands (PATTERN (i3))) != NULL)
+    return 0;
 
   if (GET_CODE (PATTERN (i3)) == PARALLEL)
     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
diff --git a/gcc/testsuite/gcc.target/arm/pr46164.c b/gcc/testsuite/gcc.target/arm/pr46164.c
new file mode 100644
index 0000000..ad3b7cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr46164.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mcpu=cortex-m3 -mthumb -O1" } */
+
+char temp[16];
+extern int foo1 (void);
+
+void foo (void)
+{
+  int i;
+  int len;
+
+  while (1)
+  {
+    len = foo1 ();
+    register char *a asm ("r1") = temp;
+    asm volatile ("mov %[r1], %[r1]\n " :: [r1]"r"(a), "m"(*a));
+
+    for (i = 0; i < len; i++)
+    {
+      if (temp[i] == 10)
+      return;
+    }
+  }
+}
+
+/* { dg-final { scan-assembler "\[\\t \]+mov\ r1,\ r1" } } */