[ARM,2/2] Load-acquire, store-release atomics in AArch32 ARMv8

Message ID	003201ce00a2$f4e9d470$debd7d50$@tkachov@arm.com
State	New
Headers	show Return-Path: <gcc-patches-return-336282-incoming=patchwork.ozlabs.org@gcc.gnu.org> Comment: DKIM? See http://www.dkim.org Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:From:To:Cc:References:In-Reply-To:Subject:Date:Message-ID:MIME-Version:X-MC-Unique:Content-Type:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=FKX/h1IRThTAaNj1PK5qbiPGDhrB+vlkZ1qk+59ApzYKFdoNy0iwv6/r6okDFx gf1EamTD9ipTmuz8W5ek8rDz2VyNEj71bOYEf3JQ7tLy+uFZTDvMwGSU5a9h6uyC HgfNGYQsxontiopWEUjNSgkWmKLJzAGd5dc7IqsUutRII=; From: "Kyrylo Tkachov" <kyrylo.tkachov@arm.com> To: <gcc-patches@gcc.gnu.org> Cc: "Ramana Radhakrishnan" <Ramana.Radhakrishnan@arm.com>, "Richard Earnshaw" <Richard.Earnshaw@arm.com>, "Marcus Shawcroft" <Marcus.Shawcroft@arm.com> References: <003101ce00a2$bd9873f0$38c95bd0$@tkachov@arm.com> In-Reply-To: <003101ce00a2$bd9873f0$38c95bd0$@tkachov@arm.com> Subject: RE: [PATCH][ARM][2/2] Load-acquire, store-release atomics in AArch32 ARMv8 Date: Fri, 1 Feb 2013 17:38:32 -0000 Message-ID: <003201ce00a2$f4e9d470$debd7d50$@tkachov@arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0033_01CE00A2.F4E9D470" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org

diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c index 1492e25..9785bca 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c @@ -1,41 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -#define STRONG 0 -#define WEAK 1 -int v = 0; - -int -atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b) -{ - return __atomic_compare_exchange (&v, &a, &b, - STRONG, __ATOMIC_RELEASE, - __ATOMIC_ACQUIRE); -} - -int -atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b) -{ - return __atomic_compare_exchange (&v, &a, &b, - WEAK, __ATOMIC_RELEASE, - __ATOMIC_ACQUIRE); -} - -int -atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b) -{ - return __atomic_compare_exchange_n (&v, &a, b, - STRONG, __ATOMIC_RELEASE, - __ATOMIC_ACQUIRE); -} - -int -atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b) -{ - return __atomic_compare_exchange_n (&v, &a, b, - WEAK, __ATOMIC_RELEASE, - __ATOMIC_ACQUIRE); -} +#include "atomic-comp-swap-release-acquire.x" /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x new file mode 100644 index 0000000..4403afd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x @@ -0,0 +1,36 @@ + +#define STRONG 0 +#define WEAK 1 +int v = 0; + +int +atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b) +{ + return __atomic_compare_exchange (&v, &a, &b, + STRONG, __ATOMIC_RELEASE, + __ATOMIC_ACQUIRE); +} + +int +atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b) +{ + return __atomic_compare_exchange (&v, &a, &b, + WEAK, __ATOMIC_RELEASE, + __ATOMIC_ACQUIRE); +} + +int +atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b) +{ + return __atomic_compare_exchange_n (&v, &a, b, + STRONG, __ATOMIC_RELEASE, + __ATOMIC_ACQUIRE); +} + +int +atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b) +{ + return __atomic_compare_exchange_n (&v, &a, b, + WEAK, __ATOMIC_RELEASE, + __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c index be6682f..8569ac0 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_ACQ_REL (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_sub_ACQ_REL (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_and_ACQ_REL (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_nand_ACQ_REL (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_xor_ACQ_REL (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_or_ACQ_REL (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); -} +#include "atomic-op-acq_rel.x" /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x new file mode 100644 index 0000000..9970bbb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_ACQ_REL (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_sub_ACQ_REL (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_and_ACQ_REL (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_nand_ACQ_REL (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_xor_ACQ_REL (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_or_ACQ_REL (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c index 023797e..57e6d57 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_ACQUIRE (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_sub_ACQUIRE (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_and_ACQUIRE (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_nand_ACQUIRE (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_xor_ACQUIRE (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_or_ACQUIRE (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE); -} +#include "atomic-op-acquire.x" /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x new file mode 100644 index 0000000..7eeb7f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_ACQUIRE (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_sub_ACQUIRE (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_and_ACQUIRE (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_nand_ACQUIRE (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_xor_ACQUIRE (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_or_ACQUIRE (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c index 8dcc4c8..d6c2aa5 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -char v = 0; - -char -atomic_fetch_add_RELAXED (char a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_sub_RELAXED (char a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_and_RELAXED (char a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_nand_RELAXED (char a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_xor_RELAXED (char a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_or_RELAXED (char a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} +#include "atomic-op-char.x" /* { dg-final { scan-assembler-times "ldxrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxrb\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x new file mode 100644 index 0000000..a543aa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x @@ -0,0 +1,37 @@ +char v = 0; + +char +atomic_fetch_add_RELAXED (char a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_sub_RELAXED (char a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_and_RELAXED (char a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_nand_RELAXED (char a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_xor_RELAXED (char a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_or_RELAXED (char a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c index e3afde2..38d6c2c 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_CONSUME (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_sub_CONSUME (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_and_CONSUME (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_nand_CONSUME (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_xor_CONSUME (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_or_CONSUME (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME); -} +#include "atomic-op-consume.x" /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x new file mode 100644 index 0000000..c6b0792 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_CONSUME (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_sub_CONSUME (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_and_CONSUME (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_nand_CONSUME (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_xor_CONSUME (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_or_CONSUME (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c index 065ccf5..9ad7a79 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_RELAXED (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_sub_RELAXED (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_and_RELAXED (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_nand_RELAXED (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_xor_RELAXED (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_or_RELAXED (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} +#include "atomic-op-int.x" /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x new file mode 100644 index 0000000..74ab632 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_RELAXED (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_sub_RELAXED (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_and_RELAXED (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_nand_RELAXED (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_xor_RELAXED (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_or_RELAXED (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c index 065ccf5..cd3fe2c 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_RELAXED (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_sub_RELAXED (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_and_RELAXED (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_nand_RELAXED (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_xor_RELAXED (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_or_RELAXED (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} +#include "atomic-op-relaxed.x" /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x new file mode 100644 index 0000000..74ab632 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_RELAXED (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_sub_RELAXED (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_and_RELAXED (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_nand_RELAXED (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_xor_RELAXED (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_or_RELAXED (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c index 3d8c49c..2fc04b2 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_RELEASE (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_sub_RELEASE (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_and_RELEASE (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_nand_RELEASE (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_xor_RELEASE (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_or_RELEASE (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE); -} +#include "atomic-op-release.x" /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x new file mode 100644 index 0000000..343f09b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_RELEASE (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_sub_RELEASE (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_and_RELEASE (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_nand_RELEASE (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_xor_RELEASE (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_or_RELEASE (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c index a8ad4f8..202d471 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_SEQ_CST (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_sub_SEQ_CST (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_and_SEQ_CST (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_nand_SEQ_CST (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_xor_SEQ_CST (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_or_SEQ_CST (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); -} +#include "atomic-op-seq_cst.x" /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x new file mode 100644 index 0000000..e654a74 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_SEQ_CST (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_sub_SEQ_CST (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_and_SEQ_CST (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_nand_SEQ_CST (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_xor_SEQ_CST (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_or_SEQ_CST (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c index 30db340..39e71c1 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -short v = 0; - -short -atomic_fetch_add_RELAXED (short a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_sub_RELAXED (short a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_and_RELAXED (short a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_nand_RELAXED (short a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_xor_RELAXED (short a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_or_RELAXED (short a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} +#include "atomic-op-short.x" /* { dg-final { scan-assembler-times "ldxrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxrh\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x new file mode 100644 index 0000000..2fd70f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x @@ -0,0 +1,37 @@ +short v = 0; + +short +atomic_fetch_add_RELAXED (short a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_sub_RELAXED (short a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_and_RELAXED (short a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_nand_RELAXED (short a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_xor_RELAXED (short a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_or_RELAXED (short a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c new file mode 100644 index 0000000..1c1028c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-comp-swap-release-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "stlex" 4 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c new file mode 100644 index 0000000..2f091f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-acq_rel.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c b/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c new file mode 100644 index 0000000..977c2fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-char.c b/gcc/testsuite/gcc.target/arm/atomic-op-char.c new file mode 100644 index 0000000..63e34c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-char.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-char.x" + +/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-consume.c b/gcc/testsuite/gcc.target/arm/atomic-op-consume.c new file mode 100644 index 0000000..8e1779e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-consume.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-consume.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-int.c b/gcc/testsuite/gcc.target/arm/atomic-op-int.c new file mode 100644 index 0000000..1476c52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-int.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-int.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c new file mode 100644 index 0000000..cae8323 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-relaxed.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-release.c b/gcc/testsuite/gcc.target/arm/atomic-op-release.c new file mode 100644 index 0000000..415f463 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-release.c @@ -0,0 +1,11 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-release.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c new file mode 100644 index 0000000..c7b93eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-seq_cst.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-short.c b/gcc/testsuite/gcc.target/arm/atomic-op-short.c new file mode 100644 index 0000000..7e5a603 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-short.c @@ -0,0 +1,11 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-short.x" + +/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ +

[ARM,2/2] Load-acquire, store-release atomics in AArch32 ARMv8

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