From patchwork Mon Sep 15 14:48:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco X-Patchwork-Id: 389389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DE01914013A for ; Tue, 16 Sep 2014 00:48:40 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=sDKQdiI+qQ9rO+Nf m16e5V4grOyWwx8wfGFgCbt4MVcY7pfcgNCos0OZ7xOd2zNL1FCYUz/po/QKDswq hWrKtZH0LhEpS0KvI4O0b87mZZROAdPB1n3nVgaXBNbUxGaacTpUD2kgOO0yxmtA iNX4u5Zo6/CM4eaizdEO/5C9lug= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=dCn9iJzfQEUGScTBbdk+YC CSCUs=; b=bF7xiXdrMwPVdHV20s1FoeLme5GOHZ/oOKpjZUspPCzz/6A1yQgx22 B9x+z+qC0vErtK57qtdZUEMc43LUL9kWbVWcZQpyrFybDLku3uHiHZ9FQ+bJ2bS4 JMgmXpRvaPQ5NK2DyUHCf8Y1So3qq/kS9cHMDl4Hxq/AiMD2iea5U= Received: (qmail 11181 invoked by alias); 15 Sep 2014 14:48:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 11170 invoked by uid 89); 15 Sep 2014 14:48:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 15 Sep 2014 14:48:32 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 15 Sep 2014 15:48:28 +0100 Received: from e103246vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Sep 2014 15:48:26 +0100 From: "Wilco Dijkstra" To: Subject: [PATCH] AArch64: Improve regmove_costs for 128-bit types Date: Mon, 15 Sep 2014 15:48:25 +0100 Message-ID: <002901cfd0f4$1ad889b0$50899d10$@com> MIME-Version: 1.0 X-MC-Unique: 114091515482801601 Hi, This patch improves the register move costs for 128-bit types. OK for commit? ChangeLog: 2014-09-15 Wilco Dijkstra * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Add register move costs for 128-bit types. --- gcc/config/aarch64/aarch64.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 51e2c70..b032e93 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5950,6 +5950,27 @@ aarch64_register_move_cost (enum machine_mode mode, return aarch64_register_move_cost (mode, from, GENERAL_REGS) + aarch64_register_move_cost (mode, GENERAL_REGS, to); + if (GET_MODE_SIZE (mode) == 16) + { + /* 128-bit operations on general registers require 2 instructions. */ + if (from == GENERAL_REGS && to == GENERAL_REGS) + return regmove_cost->GP2GP * 2; + else if (from == GENERAL_REGS) + return regmove_cost->GP2FP * 2; + else if (to == GENERAL_REGS) + return regmove_cost->FP2GP * 2; + + /* When AdvSIMD instructions are disabled it is not possible to move + a 128-bit value directly between Q registers. This is handled in + secondary reload. A general register is used as a scratch to move + the upper DI value and the lower DI value is moved directly, + hence the cost is the sum of three moves. */ + if (! TARGET_SIMD) + return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; + + return regmove_cost->FP2FP; + } + if (from == GENERAL_REGS && to == GENERAL_REGS) return regmove_cost->GP2GP; else if (from == GENERAL_REGS) @@ -5957,14 +5978,6 @@ aarch64_register_move_cost (enum machine_mode mode, else if (to == GENERAL_REGS) return regmove_cost->FP2GP; - /* When AdvSIMD instructions are disabled it is not possible to move - a 128-bit value directly between Q registers. This is handled in - secondary reload. A general register is used as a scratch to move - the upper DI value and the lower DI value is moved directly, - hence the cost is the sum of three moves. */ - if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 16) - return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; - return regmove_cost->FP2FP; }