From patchwork Thu Feb 12 11:12:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Terry Guo X-Patchwork-Id: 439166 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B58C6140129 for ; Thu, 12 Feb 2015 22:23:25 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=QO1Vd7eJzm96ZRaUkjGIpooMV9kOA2kJ6niGGkPe1gg56i3BO8 7ts609NFGCnrDca3TUeKOgCl9QEd2riur+aj2DwqrWD1vqUZR5H9sTOv8UsY4ZX7 MwLCqot78IAeXaz23Ofq1TP05lWpkA4BBdYkowCCjRXk7EOG1mTw3o7tM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=kOTliaaeW0t7dlZHAl5bHPnGiUs=; b=a/UVZei0g3h4kPLPdyRn LE4zjgCHcML4NJVyIcxaJ8Bb87jH0pIFFLyJ5FxkbTmzUwLlsAMpGjq6QVYZbRbb hnvH6pWTp0HM4JRImHMSVXtUISvua/IBdULwrDTR+hcNzQ2GyxCPW0TmhknKCGEP CQ0BelahmMR2VMUUqBkJgBA= Received: (qmail 12088 invoked by alias); 12 Feb 2015 11:12:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 12067 invoked by uid 89); 12 Feb 2015 11:12:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 12 Feb 2015 11:12:37 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by service87.mimecast.com; Thu, 12 Feb 2015 11:12:34 +0000 Received: from shawin252 ([10.164.6.128]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 12 Feb 2015 11:12:33 +0000 From: "Terry Guo" To: Cc: "Richard Earnshaw" , "Ramana Radhakrishnan" Subject: [Patch][ARM]Don't put volatile memory access in IT block for cortex-m7 Date: Thu, 12 Feb 2015 19:12:26 +0800 Message-ID: <001501d046b4$c9e32ab0$5da98010$@arm.com> MIME-Version: 1.0 X-MC-Unique: 115021211123401101 X-IsSubscribed: yes Hi there, This patch intends to prevent gcc from putting volatile memory access into IT block for target like cortex-m7. gcc/ChangeLog: 2015-02-12 Terry Guo * config/arm/arm.c (arm_tune_cortex_m7): New global variable. * config/arm/arm.h (TARGET_NO_VOLATILE_CE): New macro. (arm_tune_cortex_m7): Declare new global variable. * config/arm/arm.md (arm_comparison_operator): Disabled if not allow volatile memory access in IT block. gcc/testsuite/ChangeLog: 2015-02-12 Terry Guo * gcc.target/arm/cortex-m7-it-volatile.c: New test. diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 297dfe1..d6b854d 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -290,6 +290,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_CRC32 (arm_arch_crc) +/* Targets that don't support accessing volatile memory inside IT block. */ +#define TARGET_NO_VOLATILE_CE (arm_tune_cortex_m7) + /* The following two macros concern the ability to execute coprocessor instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently only ever tested when we know we are generating for VFP hardware; we need @@ -552,6 +555,9 @@ extern int arm_tune_wbuf; /* Nonzero if tuning for Cortex-A9. */ extern int arm_tune_cortex_a9; +/* Nonzero if tuning for Cortex-M7. */ +extern int arm_tune_cortex_m7; + /* Nonzero if we should define __THUMB_INTERWORK__ in the preprocessor. XXX This is a bit of a hack, it's intended to help work around diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7bf5b4d..081ccec 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -846,6 +846,9 @@ int arm_tune_wbuf = 0; /* Nonzero if tuning for Cortex-A9. */ int arm_tune_cortex_a9 = 0; +/* Nonzero if tuning for Cortex-M7. */ +int arm_tune_cortex_m7 = 0; + /* Nonzero if generating Thumb instructions. */ int thumb_code = 0; @@ -2859,7 +2862,8 @@ arm_option_override (void) arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0; arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0; arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0; - arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; + arm_tune_cortex_a9 = (arm_tune == cortexa9); + arm_tune_cortex_m7 = (arm_tune == cortexm7); arm_arch_crc = (insn_flags & FL_CRC32) != 0; arm_m_profile_small_mul = (insn_flags & FL_SMALLMUL) != 0; if (arm_restrict_it == 2) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index c13e9b2..164ac13 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10755,7 +10755,8 @@ [(match_operator 0 "arm_comparison_operator" [(match_operand 1 "cc_register" "") (const_int 0)])] - "TARGET_32BIT" + "TARGET_32BIT + && (!TARGET_NO_VOLATILE_CE || !volatile_refs_p (PATTERN (insn)))" "" [(set_attr "predicated" "yes")] ) diff --git a/gcc/testsuite/gcc.target/arm/cortex-m7-it-volatile.c b/gcc/testsuite/gcc.target/arm/cortex-m7-it-volatile.c new file mode 100644 index 0000000..206afdb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cortex-m7-it-volatile.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-Os -mthumb -mcpu=cortex-m7" } */ + +int +foo (int a, int b, volatile int *c, volatile int *d) +{ + if (a > b) + return c[0]; + else + return d[0]; +} + +/* { dg-final { scan-assembler-not "ldrgt" } } */