[ARM,1/n] New patterns for subtract with carry

Add patterns to handle various subtract with carry operations.

These patterns match RTL insns emitted by splitters 
for DImode operations such as subdi, negdi, and cmpdi.

gcc/

2013-02-14  Greta Yorsh  <Greta.Yorsh@arm.com>

        * config/arm/arm.md (subsi3_carryin, subsi3_carryin_const): New
patterns.
        (subsi3_carryin_compare,subsi3_carryin_compare_const): Likewise.
        (subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise.

On 18/02/13 18:35, Greta Yorsh wrote:
> Add patterns to handle various subtract with carry operations.
>
> These patterns match RTL insns emitted by splitters
> for DImode operations such as subdi, negdi, and cmpdi.
>
> gcc/
>
> 2013-02-14  Greta Yorsh  <Greta.Yorsh@arm.com>
>
>          * config/arm/arm.md (subsi3_carryin, subsi3_carryin_const): New
> patterns.
>          (subsi3_carryin_compare,subsi3_carryin_compare_const): Likewise.
>          (subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise.
>
>

Not ok.  RSC does not exist in Thumb state.

R.

> 1-patterns-subtract-with-carry.patch.txt
>
>
> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> index 35294dd6560ac63279d95eca6cf774257e06bd93..0000000000000000000000000000000000000000 100644
> --- a/gcc/config/arm/arm.md
> +++ b/gcc/config/arm/arm.md
> @@ -1019,3 +1019,86 @@ (define_insn "*addsi3_carryin_clobercc_<
>      [(set_attr "conds" "set")]
>   )
>
> +(define_insn "*subsi3_carryin"
> +  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
> +        (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I")
> +                            (match_operand:SI 2 "s_register_operand" "r,r"))
> +                  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
> +  "TARGET_32BIT"
> +  "@
> +   sbc%?\\t%0, %1, %2
> +   rsc%?\\t%0, %2, %1"
> +  [(set_attr "conds" "use")
> +   (set_attr "predicable" "yes")]
> +)
> +
> +(define_insn "*subsi3_carryin_const"
> +  [(set (match_operand:SI 0 "s_register_operand" "=r")
> +        (minus:SI (plus:SI (match_operand:SI 1 "reg_or_int_operand" "r")
> +                           (match_operand:SI 2 "arm_not_operand" "K"))
> +                  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
> +  "TARGET_32BIT"
> +  "sbc\\t%0, %1, #%B2"
> +  [(set_attr "conds" "use")]
> +)
> +
> +(define_insn "*subsi3_carryin_compare"
> +  [(set (reg:CC CC_REGNUM)
> +        (compare:CC (match_operand:SI 1 "s_register_operand" "r")
> +                    (match_operand:SI 2 "s_register_operand" "r")))
> +   (set (match_operand:SI 0 "s_register_operand" "=r")
> +        (minus:SI (minus:SI (match_dup 1)
> +                            (match_dup 2))
> +                  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
> +  "TARGET_32BIT"
> +  "sbcs\\t%0, %1, %2"
> +  [(set_attr "conds" "set")]
> +)
> +
> +(define_insn "*subsi3_carryin_compare_const"
> +  [(set (reg:CC CC_REGNUM)
> +        (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r")
> +                    (match_operand:SI 2 "arm_not_operand" "K")))
> +   (set (match_operand:SI 0 "s_register_operand" "=r")
> +        (minus:SI (plus:SI (match_dup 1)
> +                           (match_dup 2))
> +                  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
> +  "TARGET_32BIT"
> +  "sbcs\\t%0, %1, #%B2"
> +  [(set_attr "conds" "set")]
> +)
> +
> +(define_insn "*subsi3_carryin_shift"
> +  [(set (match_operand:SI 0 "s_register_operand" "=r")
> +	(minus:SI (minus:SI
> +		  (match_operand:SI 1 "s_register_operand" "r")
> +                  (match_operator:SI 2 "shift_operator"
> +                   [(match_operand:SI 3 "s_register_operand" "r")
> +                    (match_operand:SI 4 "reg_or_int_operand" "rM")]))
> +                 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
> +  "TARGET_32BIT"
> +  "sbc%?\\t%0, %1, %3%S2"
> +  [(set_attr "conds" "use")
> +   (set_attr "predicable" "yes")
> +   (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
> +		      (const_string "alu_shift")
> +                     (const_string "alu_shift_reg")))]
> +)
> +
> +(define_insn "*rsbsi3_carryin_shift"
> +  [(set (match_operand:SI 0 "s_register_operand" "=r")
> +	(minus:SI (minus:SI
> +                  (match_operator:SI 2 "shift_operator"
> +                   [(match_operand:SI 3 "s_register_operand" "r")
> +                    (match_operand:SI 4 "reg_or_int_operand" "rM")])
> +		   (match_operand:SI 1 "s_register_operand" "r"))
> +                 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
> +  "TARGET_32BIT"
> +  "rsc%?\\t%0, %1, %3%S2"
> +  [(set_attr "conds" "use")
> +   (set_attr "predicable" "yes")
> +   (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
> +		      (const_string "alu_shift")
> +		      (const_string "alu_shift_reg")))]
> +)
> +
>

On 04/05/13 16:26, Greta Yorsh wrote:
>
>> -----Original Message-----
>> From: Richard Earnshaw
>> Sent: 22 February 2013 16:30
>> To: Greta Yorsh
>> Cc: GCC Patches; Ramana Radhakrishnan; nickc@redhat.com;
>> paul@codesourcery.com
>> Subject: Re: [PATCH,ARM][1/n] New patterns for subtract with carry
>>
>> On 18/02/13 18:35, Greta Yorsh wrote:
>>> Add patterns to handle various subtract with carry operations.
>>>
>>> These patterns match RTL insns emitted by splitters
>>> for DImode operations such as subdi, negdi, and cmpdi.
>>>
>>> gcc/
>>>
>>> 2013-02-14  Greta Yorsh  <Greta.Yorsh@arm.com>
>>>
>>>           * config/arm/arm.md (subsi3_carryin, subsi3_carryin_const):
>> New
>>> patterns.
>>>           (subsi3_carryin_compare,subsi3_carryin_compare_const):
>> Likewise.
>>>           (subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise.
>>>
>>>
>>
>> Not ok.  RSC does not exist in Thumb state.
>>
>> R.
>
> I'm attaching an updated patch. I changed the condition of rsbsi3_carryin_shift pattern and added "arch" attribute to subsi3_carryin as appropriate.
>
> I have also tested the patch again on the recent trunk along with all other patching in this series, which have already been approved. No regressions.
>
> Ok for trunk?
>

Ok

ramana