From patchwork Thu Nov 19 18:12:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 546883 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 88048140D7C for ; Fri, 20 Nov 2015 21:41:02 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=caDsJt9K; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=tynxcXu29V2ocIll bYvOcSfS6c2Wu4MqueVhgslqb/4ju2FgipVdsPvayg7UE8pwx0v7zJeSPuFhI8CI +bQ78RORFPpXSx4sgfZA43n1v1iLjcxGzZjbg7v5BfDpO2UBXUw0WGqqbTB3Xtz/ F9T0qoDLwbEY7v9Hrnjmc0zozUk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=EyOw0y4jItD2voDcVmr5O6 rGt6o=; b=caDsJt9KBKP0G/1FkROqpeS7hP5+hsPhHXUP2PH4q92Pk2ElpL7hu1 nx2TDoJVqnFGVHEM0KhrnlE4PJnLtB22fjqLVIzPLU1qOrjmAXoovguhmURDA0Hi gVDpzmvrswUx+qarw5QqayIYcoij7/NY5A1I0gIpDHkPqHMT6y2PU= Received: (qmail 83668 invoked by alias); 20 Nov 2015 10:40:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 83654 invoked by uid 89); 20 Nov 2015 10:40:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, DATE_IN_PAST_12_24, SPF_PASS autolearn=no version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 20 Nov 2015 10:40:52 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-27-J8J0PF-1So2dcJNzz5znWA-1; Fri, 20 Nov 2015 10:40:47 +0000 Received: from E107166VM ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 20 Nov 2015 10:40:47 +0000 From: "Wilco Dijkstra" To: Subject: [PATCH][ARM] Enable fusion of AES instructions Date: Thu, 19 Nov 2015 18:12:23 -0000 Message-ID: <000901d122f5$d6c67fc0$84537f40$@arm.com> MIME-Version: 1.0 X-MC-Unique: J8J0PF-1So2dcJNzz5znWA-1 Enable instruction fusion of AES instructions on ARM for Cortex-A53 and Cortex-A57. OK for commit? ChangeLog: 2015-11-20 Wilco Dijkstra * gcc/config/arm/arm.c (arm_cortex_a53_tune): Add AES fusion. (arm_cortex_a57_tune): Likewise. (aarch_macro_fusion_pair_p): Add support for AES fusion. * gcc/config/arm/arm-protos.h (fuse_ops): Add FUSE_AES_AESMC. --- gcc/config/arm/arm-protos.h | 5 +++-- gcc/config/arm/arm.c | 9 +++++++-- 2 files changed, 10 insertions(+), 4 deletions(-) } diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index f9b1276..4801bb8 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -302,8 +302,9 @@ struct tune_params enum fuse_ops { FUSE_NOTHING = 0, - FUSE_MOVW_MOVT = 1 << 0 - } fusible_ops: 1; + FUSE_MOVW_MOVT = 1 << 0, + FUSE_AES_AESMC = 1 << 1 + } fusible_ops: 2; /* Depth of scheduling queue to check for L2 autoprefetcher. */ enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL} sched_autopref: 2; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 02f5dc3..7077199 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1969,7 +1969,7 @@ const struct tune_params arm_cortex_a53_tune = tune_params::DISPARAGE_FLAGS_NEITHER, tune_params::PREF_NEON_64_FALSE, tune_params::PREF_NEON_STRINGOPS_TRUE, - FUSE_OPS (tune_params::FUSE_MOVW_MOVT), + FUSE_OPS (tune_params::FUSE_MOVW_MOVT | tune_params::FUSE_AES_AESMC), tune_params::SCHED_AUTOPREF_OFF }; @@ -1992,7 +1992,7 @@ const struct tune_params arm_cortex_a57_tune = tune_params::DISPARAGE_FLAGS_ALL, tune_params::PREF_NEON_64_FALSE, tune_params::PREF_NEON_STRINGOPS_TRUE, - FUSE_OPS (tune_params::FUSE_MOVW_MOVT), + FUSE_OPS (tune_params::FUSE_MOVW_MOVT | tune_params::FUSE_AES_AESMC), tune_params::SCHED_AUTOPREF_FULL }; @@ -29668,6 +29668,11 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr) && REGNO (SET_DEST (curr_set)) == REGNO (SET_DEST (prev_set))) return true; } + + if (current_tune->fusible_ops & tune_params::FUSE_AES_AESMC + && aarch_crypto_can_dual_issue (prev, curr)) + return true; + return false;