From patchwork Mon Nov 24 13:46:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco X-Patchwork-Id: 413729 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 28F74140185 for ; Tue, 25 Nov 2014 00:47:07 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:references:in-reply-to:subject:date:message-id :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=qucNDzclX0MSiChzSWpBM3Pq8/Skrc1x+Ys7AO59/uS1J6UC2OqbA L2actUh6VD2fbb/xF/VYBm9HDuvZYj8bWDI4fyqXi6bw2EZ/nVb7LTOTGYu8tdrx g2Df7KuA2AkN/9WTr12QAF1SXTR/4rbVHQN1CZMjhSGJB4LhOANE14= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:references:in-reply-to:subject:date:message-id :mime-version:content-type:content-transfer-encoding; s=default; bh=79wCy/dP+LZ2nL3jTzDiOgfWXWo=; b=h/aby66Dp9MzI0ttZH8gzil8IgKX DRkyKdksuv+A/fCNDOKWhJ8nqA2A3v9rvMnjI1rtS/Zd4fqm1Di96k39s5ZHoPJh fxIdDnfkg/uWuUcBeISLIasU2Wr1lQ4YFM6RGmbsCc8YSjoJ4I1kT0u0C5EN8eKA i+k0SHOytqWLFsc= Received: (qmail 6075 invoked by alias); 24 Nov 2014 13:46:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6058 invoked by uid 89); 24 Nov 2014 13:46:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 24 Nov 2014 13:46:56 +0000 Received: from cam-owa1.Emea.Arm.com (217.140.96.140 [217.140.96.140]) by service87.mimecast.com; Mon, 24 Nov 2014 13:46:54 +0000 Received: from e103246vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 24 Nov 2014 13:46:53 +0000 From: "Wilco Dijkstra" To: "Richard Earnshaw" , Cc: References: <002101cff377$9fcb6ac0$df624040$@com> <545CDAE1.6050900@arm.com> In-Reply-To: <545CDAE1.6050900@arm.com> Subject: RE: [PATCH] AArch64: Add TARGET_SCHED_REASSOCIATION_WIDTH Date: Mon, 24 Nov 2014 13:46:51 -0000 Message-ID: <000601d007ed$1a453090$4ecf91b0$@com> MIME-Version: 1.0 X-MC-Unique: 114112413465400301 > Richard Earnshaw wrote: > If all cores seem to benefit from FP reassociation set to 4, then it > seems odd that 4 is not also the default for generic. > > Andrew, you may need to pick a target-specific value for ThunderX; I > think Wilco has just picked something that seems plausible because he > needs to put a real value in there. > > What happens if the integer and vector numbers are bumped up? I'd have > thought that integer numbers >1 would be appropriate on all dual-issue > or greater cores. I tried int and vector as well, and setting int to 2 did give an improvement, but vector had no effect, so I'll leave to 1 for now. The patch is the same as last time, it just sets integer to 2, and uses the same settings for all CPUs. OK for commit? ChangeLog: 2014-11-24 Wilco Dijkstra * gcc/config/aarch64/aarch64-protos.h (tune-params): Add reasociation tuning parameters. * gcc/config/aarch64/aarch64.c (TARGET_SCHED_REASSOCIATION_WIDTH): Define. (aarch64_reassociation_width): New function. (generic_tunings) Add reassociation tuning parameters. (cortexa53_tunings): Likewise. (cortexa57_tunings): Likewise. (thunderx_tunings): Likewise. --- gcc/config/aarch64/aarch64-protos.h | 3 +++ gcc/config/aarch64/aarch64.c | 36 ++++++++++++++++++++++++++++++++---- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index a9985b5..ac3487b 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -170,6 +170,9 @@ struct tune_params const struct cpu_vector_cost *const vec_costs; const int memmov_cost; const int issue_rate; + const int int_reassoc_width; + const int fp_reassoc_width; + const int vec_reassoc_width; }; HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3832123..e543161 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -314,7 +314,10 @@ static const struct tune_params generic_tunings = &generic_regmove_cost, &generic_vector_cost, NAMED_PARAM (memmov_cost, 4), - NAMED_PARAM (issue_rate, 2) + NAMED_PARAM (issue_rate, 2), + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1 /* vec_reassoc_width. */ }; static const struct tune_params cortexa53_tunings = @@ -324,7 +327,10 @@ static const struct tune_params cortexa53_tunings = &cortexa53_regmove_cost, &generic_vector_cost, NAMED_PARAM (memmov_cost, 4), - NAMED_PARAM (issue_rate, 2) + NAMED_PARAM (issue_rate, 2), + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1 /* vec_reassoc_width. */ }; static const struct tune_params cortexa57_tunings = @@ -334,7 +340,10 @@ static const struct tune_params cortexa57_tunings = &cortexa57_regmove_cost, &cortexa57_vector_cost, NAMED_PARAM (memmov_cost, 4), - NAMED_PARAM (issue_rate, 3) + NAMED_PARAM (issue_rate, 3), + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1 /* vec_reassoc_width. */ }; static const struct tune_params thunderx_tunings = @@ -344,7 +353,10 @@ static const struct tune_params thunderx_tunings = &thunderx_regmove_cost, &generic_vector_cost, NAMED_PARAM (memmov_cost, 6), - NAMED_PARAM (issue_rate, 2) + NAMED_PARAM (issue_rate, 2), + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1 /* vec_reassoc_width. */ }; /* A processor implementing AArch64. */ @@ -437,6 +449,19 @@ static const char * const aarch64_condition_codes[] = "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" }; +static int +aarch64_reassociation_width (unsigned opc ATTRIBUTE_UNUSED, + enum machine_mode mode) +{ + if (VECTOR_MODE_P (mode)) + return aarch64_tune_params->vec_reassoc_width; + if (INTEGRAL_MODE_P (mode)) + return aarch64_tune_params->int_reassoc_width; + if (FLOAT_MODE_P (mode)) + return aarch64_tune_params->fp_reassoc_width; + return 1; +} + /* Provide a mapping from gcc register numbers to dwarf register numbers. */ unsigned aarch64_dbx_register_number (unsigned regno) @@ -10499,6 +10524,9 @@ aarch64_gen_ccmp_next (rtx prev, int cmp_code, rtx op0, rtx op1, int bit_code) #undef TARGET_PREFERRED_RELOAD_CLASS #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class +#undef TARGET_SCHED_REASSOCIATION_WIDTH +#define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width + #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload