From patchwork Mon Mar 17 03:35:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Terry Guo X-Patchwork-Id: 330753 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1D1CE2C0097 for ; Mon, 17 Mar 2014 14:36:00 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=VJUwB/85MG7eZiUTdMGbf5QYr8gqreyB+BGSSSHn3zLFvC7hZS 1r8Y70kd1XlEoYpCoBAhlv0K0MzvX8ShFZxRJc7wALOx2lCsyW/lb0/FOIjqH7ZW 8gX4HvLq77nNPbLgjUEfYzCXk3F2GLm9cS6zUcrpbM3S+9HAuK3YNryis= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=Gg0xciitCAKlVh3uS+Ji2RZ34xo=; b=LKH5GEumPAuz40ZOqJlO Fmgy3QfhA9qpb9EhRQ1xmEY0uhX+KEzKSG1PJMK7lnZbltcpJoUe/VNmhsrd+y8j M6Tj4JCcHhwIyBvuxKBkuK6nGPkWE2QNyRK2Yrn/T+LKEf1JOB1JETXJzg1F8mtu sVbFXz5VMNaFXOlNPqHQYO8= Received: (qmail 18320 invoked by alias); 17 Mar 2014 03:35:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 18302 invoked by uid 89); 17 Mar 2014 03:35:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 17 Mar 2014 03:35:47 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 17 Mar 2014 03:35:44 +0000 Received: from shawin053 ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 17 Mar 2014 03:35:54 +0000 From: "Terry Guo" To: Cc: "Ramana Radhakrishnan" , "Richard Earnshaw" Subject: [PATCH, GCC/THUMB1] New define_insn_and_split pattern to enable optimizing out certain unnecessary uxtb instruction Date: Mon, 17 Mar 2014 11:35:51 +0800 Message-ID: <000401cf4192$00bc12f0$023438d0$@arm.com> MIME-Version: 1.0 X-MC-Unique: 114031703354402701 X-IsSubscribed: yes Hi The existing test case gcc.target/arm/unsigned-extend-1.c fails for Thumb1 target like cortex-m0 because the thumb1_addsi3_addgeu insn pattern isn't friendly to gcc combine pass. Before combine pass, we have such insn for this test case: (insn 10 9 12 2 (set (reg:SI 118) (plus:SI (plus:SI (reg:SI 120) (reg:SI 120)) (geu:SI (reg:SI 119) (reg:SI 117)))) When the operand (reg:SI 120) is zero and operand (reg:SI 119) is constant 9, combine pass will turn this insn into: (insn 10 9 12 2 (set (reg:SI 118) (leu:SI (reg:SI 116) (const_int 9)))) Unfortunately this new insn doesn't match any existing patterns, this causes combine pass to undo all attempts and results in sub-optimal code. The attached patch intends to legitimize the new insn. Tested with gcc regression test and no new regression. Is it OK to trunk? BR, Terry 2014-03-17 Terry Guo * config/arm/arm.md (cstoresi_leu_thumb1): New define_insn_and_split pattern. (cstoresi4): Use above new pattern. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 2ddda02..905a5b8 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -8755,18 +8755,14 @@ case LEU: op3 = force_reg (SImode, operands[3]); - scratch = force_reg (SImode, const0_rtx); - emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch, - op3, operands[2])); + emit_insn (gen_cstoresi_leu_thumb1 (operands[0], operands[2], op3)); break; case GEU: op3 = operands[3]; if (!thumb1_cmp_operand (op3, SImode)) op3 = force_reg (SImode, op3); - scratch = force_reg (SImode, const0_rtx); - emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch, - operands[2], op3)); + emit_insn (gen_cstoresi_leu_thumb1 (operands[0], op3, operands[2])); break; case LTU: @@ -8909,6 +8905,34 @@ (set_attr "type" "multiple")] ) +(define_insn_and_split "cstoresi_leu_thumb1" + [(set (match_operand:SI 0 "s_register_operand" "=l") + (leu:SI (match_operand:SI 1 "s_register_operand" "l") + (match_operand:SI 2 "thumb1_cmp_operand" "lI")))] + "TARGET_THUMB1" + "#" + "TARGET_THUMB1" + [(set (match_dup 3) (const_int 0)) + (set (match_dup 0) + (plus:SI (plus:SI (match_dup 3) + (match_dup 3)) + (geu:SI (match_dup 4) + (match_dup 1))))] + " + operands[3] = gen_reg_rtx (SImode); + + if (CONST_INT_P (operands[2])) + { + operands[4] = gen_reg_rtx (SImode); + emit_move_insn (operands[4], operands[2]); + } + else + operands[4] = operands[2]; + " + [(set_attr "length" "4") + (set_attr "type" "multiple")] +) + ;; Conditional move insns