From patchwork Thu May 8 17:36:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Bolton X-Patchwork-Id: 347146 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9E2F514009E for ; Fri, 9 May 2014 03:36:29 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=TlL78CyhxaCeUH5cAa86Kkoo+LK+EJfzwDyNutDBhYRMW0D6TVD24 uEfm3A6muFTEGmwHG389HUpUqHttG1nLxsbLvkha8y7qakniNHi2rqtGGC+Cg1lk 9T3SlB1G0tpW3ohU8B6bOiTVuMu/yrVz3deZSujNdQGxM/71+tQ0Gg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=cR4Jpsrnb7Mfcj7pk5x85nfMtz8=; b=OTESHgg1QhWy/IHDTuSm fD2iD3hd1FQcsK73NGj7Wld3QZkS/EvuHzCkDNg3iLW953wFvLPkHR5nzFeeixPD GMjUN1IGcig2/h03N/po96KuhhLq0qqnpXHDoy/cR456fUyzAxKpeCl4l7RvNsG5 zswXTH8y9pH6DPAmaYC+fhQ= Received: (qmail 23474 invoked by alias); 8 May 2014 17:36:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 23463 invoked by uid 89); 8 May 2014 17:36:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 May 2014 17:36:20 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 08 May 2014 18:36:17 +0100 Received: from e104535vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 May 2014 18:36:24 +0100 From: "Ian Bolton" To: "gcc-patches" Subject: [PATCH, AArch64] Use MOVN to generate 64-bit negative immediates where sensible Date: Thu, 8 May 2014 18:36:19 +0100 Message-ID: <000001cf6ae4$059c2280$10d46780$@bolton@arm.com> MIME-Version: 1.0 x-cr-hashedpuzzle: ANtx A5IW A8Fp BUVg CnX9 DVNJ Dco9 Dqfd Dupt D24b ERlW HzQU I++E JaJa KbWh K0Y6; 1; ZwBjAGMALQBwAGEAdABjAGgAZQBzAEAAZwBjAGMALgBnAG4AdQAuAG8AcgBnAA==; Sosha1_v1; 7; {0633F682-B32F-4471-8A2F-856B1BB2C62F}; aQBhAG4ALgBiAG8AbAB0AG8AbgBAAGEAcgBtAC4AYwBvAG0A; Thu, 08 May 2014 17:36:17 GMT; WwBQAEEAVABDAEgALAAgAEEAQQByAGMAaAA2ADQAXQAgAFUAcwBlACAATQBPAFYATgAgAHQAbwAgAGcAZQBuAGUAcgBhAHQAZQAgADYANAAtAGIAaQB0ACAAbgBlAGcAYQB0AGkAdgBlACAAaQBtAG0AZQBkAGkAYQB0AGUAcwAgAHcAaABlAHIAZQAgAHMAZQBuAHMAaQBiAGwAZQA= x-cr-puzzleid: {0633F682-B32F-4471-8A2F-856B1BB2C62F} X-MC-Unique: 114050818361702001 X-IsSubscribed: yes Hi, It currently takes 4 instructions to generate certain immediates on AArch64 (unless we put them in the constant pool). For example ... long long ffffbeefcafebabe () { return 0xFFFFBEEFCAFEBABEll; } leads to ... mov x0, 0x47806 mov x0, 0xcafe, lsl 16 mov x0, 0xbeef, lsl 32 orr x0, x0, -281474976710656 The above case is tackled in this patch by employing MOVN to generate the top 32-bits in a single instruction ... mov x0, -71536975282177 movk x0, 0xcafe, lsl 16 movk x0, 0xbabe, lsl 0 Note that where at least two half-words are 0xffff, existing code that does the immediate in two instructions is still used.) Tested on standard gcc regressions and the attached test case. OK for commit? Cheers, Ian 2014-05-08 Ian Bolton gcc/ * config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Use MOVN when top-most half-word (and only that half-word) is 0xffff. gcc/testsuite/ * gcc.target/aarch64/movn_1.c: New test. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 43a83566..a8e504e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1177,6 +1177,18 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm) } } + /* Look for case where upper 16 bits are set, so we can use MOVN. */ + if ((val & 0xffff000000000000ll) == 0xffff000000000000ll) + { + emit_insn (gen_rtx_SET (VOIDmode, dest, + GEN_INT (~ (~val & (0xffffll << 32))))); + emit_insn (gen_insv_immdi (dest, GEN_INT (16), + GEN_INT ((val >> 16) & 0xffff))); + emit_insn (gen_insv_immdi (dest, GEN_INT (0), + GEN_INT (val & 0xffff))); + return; + } + simple_sequence: first = true; mask = 0xffff; diff --git a/gcc/testsuite/gcc.target/aarch64/movn_1.c b/gcc/testsuite/gcc.target/aarch64/movn_1.c new file mode 100644 index 0000000..cc11ade --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/movn_1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-inline --save-temps" } */ + +extern void abort (void); + +long long +foo () +{ + /* { dg-final { scan-assembler "mov\tx\[0-9\]+, -71536975282177" } } */ + return 0xffffbeefcafebabell; +} + +long long +merge4 (int a, int b, int c, int d) +{ + return ((long long) a << 48 | (long long) b << 32 + | (long long) c << 16 | (long long) d); +} + +int main () +{ + if (foo () != merge4 (0xffff, 0xbeef, 0xcafe, 0xbabe)) + abort (); + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */