@@ -272,6 +272,11 @@ struct tune_params
const struct cpu_vec_costs* vec_costs;
/* Prefer Neon for 64-bit bitops. */
bool prefer_neon_for_64bits;
+ /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */
+ bool disparage_flag_setting_t16_encodings;
+ /* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags
+ would be set. */
+ bool disparage_partial_flag_setting_t16_encodings;
};
extern const struct tune_params *current_tune;
@@ -1481,7 +1481,8 @@ const struct tune_params arm_slowmul_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_fastmul_tune =
@@ -1497,7 +1498,8 @@ const struct tune_params arm_fastmul_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
/* StrongARM has early execution of branches, so a sequence that is worth
@@ -1516,7 +1518,8 @@ const struct tune_params arm_strongarm_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_xscale_tune =
@@ -1532,7 +1535,8 @@ const struct tune_params arm_xscale_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_9e_tune =
@@ -1548,7 +1552,8 @@ const struct tune_params arm_9e_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_v6t2_tune =
@@ -1564,7 +1569,8 @@ const struct tune_params arm_v6t2_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
/* Generic Cortex tuning. Use more specific tunings if appropriate. */
@@ -1581,7 +1587,8 @@ const struct tune_params arm_cortex_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_cortex_a7_tune =
@@ -1597,7 +1604,8 @@ const struct tune_params arm_cortex_a7_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_cortex_a15_tune =
@@ -1613,7 +1621,8 @@ const struct tune_params arm_cortex_a15_tune =
true, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ true, true /* Prefer 32-bit encodings. */
};
const struct tune_params arm_cortex_a53_tune =
@@ -1629,7 +1638,8 @@ const struct tune_params arm_cortex_a53_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
/* Branches can be dual-issued on Cortex-A5, so conditional execution is
@@ -1648,7 +1658,8 @@ const struct tune_params arm_cortex_a5_tune =
false, /* Prefer LDRD/STRD. */
{false, false}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_cortex_a9_tune =
@@ -1664,7 +1675,8 @@ const struct tune_params arm_cortex_a9_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_cortex_a12_tune =
@@ -1703,7 +1715,8 @@ const struct tune_params arm_v7m_tune =
false, /* Prefer LDRD/STRD. */
{false, false}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
/* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
@@ -1721,7 +1734,8 @@ const struct tune_params arm_v6m_tune =
false, /* Prefer LDRD/STRD. */
{false, false}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
const struct tune_params arm_fa726te_tune =
@@ -1737,7 +1751,8 @@ const struct tune_params arm_fa726te_tune =
false, /* Prefer LDRD/STRD. */
{true, true}, /* Prefer non short circuit. */
&arm_default_vec_cost, /* Vectorizer costs. */
- false /* Prefer Neon for 64-bits bitops. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false /* Prefer 32-bit encodings. */
};
@@ -16763,9 +16778,20 @@ thumb2_reorg (void)
compute_bb_for_insn ();
df_analyze ();
+ enum Convert_Action {SKIP, CONV, SWAP_CONV};
+
FOR_EACH_BB_FN (bb, cfun)
{
+ if (current_tune->disparage_flag_setting_t16_encodings
+ && optimize_bb_for_speed_p (bb))
+ continue;
+
rtx insn;
+ Convert_Action action = SKIP;
+ Convert_Action action_for_partial_flag_setting
+ = (current_tune->disparage_partial_flag_setting_t16_encodings
+ && optimize_bb_for_speed_p (bb))
+ ? SKIP : CONV;
COPY_REG_SET (&live, DF_LR_OUT (bb));
df_simulate_initialize_backwards (bb, &live);
@@ -16775,7 +16801,7 @@ thumb2_reorg (void)
&& !REGNO_REG_SET_P (&live, CC_REGNUM)
&& GET_CODE (PATTERN (insn)) == SET)
{
- enum {SKIP, CONV, SWAP_CONV} action = SKIP;
+ action = SKIP;
rtx pat = PATTERN (insn);
rtx dst = XEXP (pat, 0);
rtx src = XEXP (pat, 1);
@@ -16856,10 +16882,11 @@ thumb2_reorg (void)
/* ANDS <Rdn>,<Rm> */
if (rtx_equal_p (dst, op0)
&& low_register_operand (op1, SImode))
- action = CONV;
+ action = action_for_partial_flag_setting;
else if (rtx_equal_p (dst, op1)
&& low_register_operand (op0, SImode))
- action = SWAP_CONV;
+ action = action_for_partial_flag_setting == SKIP
+ ? SKIP : SWAP_CONV;
break;
case ASHIFTRT:
@@ -16870,26 +16897,30 @@ thumb2_reorg (void)
/* LSLS <Rdn>,<Rm> */
if (rtx_equal_p (dst, op0)
&& low_register_operand (op1, SImode))
- action = CONV;
+ action = action_for_partial_flag_setting;
/* ASRS <Rd>,<Rm>,#<imm5> */
/* LSRS <Rd>,<Rm>,#<imm5> */
/* LSLS <Rd>,<Rm>,#<imm5> */
else if (low_register_operand (op0, SImode)
&& CONST_INT_P (op1)
&& IN_RANGE (INTVAL (op1), 0, 31))
- action = CONV;
+ action = action_for_partial_flag_setting;
break;
case ROTATERT:
/* RORS <Rdn>,<Rm> */
if (rtx_equal_p (dst, op0)
&& low_register_operand (op1, SImode))
- action = CONV;
+ action = action_for_partial_flag_setting;
break;
case NOT:
- case NEG:
/* MVNS <Rd>,<Rm> */
+ if (low_register_operand (op0, SImode))
+ action = action_for_partial_flag_setting;
+ break;
+
+ case NEG:
/* NEGS <Rd>,<Rm> (a.k.a RSBS) */
if (low_register_operand (op0, SImode))
action = CONV;
@@ -16899,7 +16930,7 @@ thumb2_reorg (void)
/* MOVS <Rd>,#<imm8> */
if (CONST_INT_P (src)
&& IN_RANGE (INTVAL (src), 0, 255))
- action = CONV;
+ action = action_for_partial_flag_setting;
break;
case REG: