diff mbox

[AArch64] Support NEG in vector registers for DI and SI mode

Message ID 000001ce87a1$1b2c3710$5184a530$@bolton@arm.com
State New
Headers show

Commit Message

Ian Bolton July 23, 2013, 12:35 p.m. UTC 
Support added for scalar NEG instruction in vector registers.

Execution testcase included.

Tested on usual GCC Linux regressions.

OK for trunk?

Cheers,
Ian


2013-07-23  Ian Bolton  <ian.bolton@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (neg<mode>2): Offer alternative
	that uses vector registers.

testsuite/
	* gcc.target/aarch64/neg_1.c: New test.
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index e88e5be..d76056c 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2004,12 +2004,17 @@ 
 )
 
 (define_insn "neg<mode>2"
-  [(set (match_operand:GPI 0 "register_operand" "=r")
-	(neg:GPI (match_operand:GPI 1 "register_operand" "r")))]
+  [(set (match_operand:GPI 0 "register_operand" "=r,w")
+	(neg:GPI (match_operand:GPI 1 "register_operand" "r,w")))]
   ""
-  "neg\\t%<w>0, %<w>1"
+  "@
+   neg\\t%<w>0, %<w>1
+   neg\\t%<rtn>0<vas>, %<rtn>1<vas>"
   [(set_attr "v8type" "alu")
-   (set_attr "mode" "<MODE>")]
+   (set_attr "simd_type" "*,simd_negabs")
+   (set_attr "simd" "*,yes")
+   (set_attr "mode" "<MODE>")
+   (set_attr "simd_mode" "<MODE>")]
 )
 
 ;; zero_extend version of above
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8e40c5d..7acbcfd 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -277,6 +277,12 @@ 
 		    (V2DI "") (V2SF "")
 		    (V4SF "") (V2DF "")])
 
+;; Register Type Name and Vector Arrangement Specifier for when
+;; we are doing scalar for DI and SIMD for SI (ignoring all but
+;; lane 0).
+(define_mode_attr rtn [(DI "d") (SI "")])
+(define_mode_attr vas [(DI "") (SI ".2s")])
+
 ;; Map a floating point mode to the appropriate register name prefix
 (define_mode_attr s [(SF "s") (DF "d")])
 
diff --git a/gcc/testsuite/gcc.target/aarch64/neg_1.c b/gcc/testsuite/gcc.target/aarch64/neg_1.c
new file mode 100644
index 0000000..04b0fdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/neg_1.c
@@ -0,0 +1,67 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline --save-temps" } */
+
+extern void abort (void);
+
+long long
+neg64 (long long a)
+{
+  /* { dg-final { scan-assembler "neg\tx\[0-9\]+" } } */
+  return 0 - a;
+}
+
+long long
+neg64_in_dreg (long long a)
+{
+  /* { dg-final { scan-assembler "neg\td\[0-9\]+, d\[0-9\]+" } } */
+  register long long x asm ("d8") = a;
+  register long long y asm ("d9");
+  asm volatile ("" : : "w" (x));
+  y = 0 - x;
+  asm volatile ("" : : "w" (y));
+  return y;
+}
+
+int
+neg32 (int a)
+{
+  /* { dg-final { scan-assembler "neg\tw\[0-9\]+" } } */
+  return 0 - a;
+}
+
+int
+neg32_in_sreg (int a)
+{
+  /* { dg-final { scan-assembler "neg\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+  register int x asm ("s8") = a;
+  register int y asm ("s9");
+  asm volatile ("" : : "w" (x));
+  y = 0 - x;
+  asm volatile ("" : : "w" (y));
+  return y;
+}
+
+int
+main (void)
+{
+  long long a;
+  int b;
+  a = 61;
+  b = 313;
+
+  if (neg64 (a) != -61)
+    abort ();
+
+  if (neg64_in_dreg (a) != -61)
+    abort ();
+
+  if (neg32 (b) != -313)
+    abort ();
+
+  if (neg32_in_sreg (b) != -313)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */