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[ARM] remove incscc and decscc patterns

Message ID 000001cdfb16$9a6e3ae0$cf4ab0a0$@yorsh@arm.com
State New
Headers show

Commit Message

Greta Yorsh Jan. 25, 2013, 4:11 p.m. UTC 
Ping?

Thanks,
Greta

> -----Original Message-----
> From: Greta Yorsh [mailto:greta.yorsh@arm.com]
> Sent: 18 January 2013 11:44
> To: GCC Patches
> Cc: richard.sandiford@linaro.org; Ramana Radhakrishnan; Richard
> Earnshaw
> Subject: [PATCH,ARM] remove incscc and decscc patterns
> 
> Remove incscc and decscc expanders that appear to be dead, along with
> the
> related patterns.
> 
> This patch is a follow up on:
> http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01128.html
> 
> No regression qemu for arm-none-eabi. Bootstrap successful.
> 
> Ok for trunk?
> 
> Thanks,
> Greta
> 
> 2013-01-17  Greta Yorsh  <Greta.Yorsh@arm.com>
> 
> 	* config/arm/arm.md (incscc,arm_incscc,decscc,arm_decscc):
> Delete.
diff mbox

Patch

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index de57f40..80480a0 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1015,28 +1015,6 @@ 
    [(set_attr "conds" "set")]
 )
 
-(define_expand "incscc"
-  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
-        (plus:SI (match_operator:SI 2 "arm_comparison_operator"
-                    [(match_operand:CC 3 "cc_register" "") (const_int 0)])
-                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
-  "TARGET_32BIT"
-  ""
-)
-
-(define_insn "*arm_incscc"
-  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
-        (plus:SI (match_operator:SI 2 "arm_comparison_operator"
-                    [(match_operand:CC 3 "cc_register" "") (const_int 0)])
-                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
-  "TARGET_ARM"
-  "@
-  add%d2\\t%0, %1, #1
-  mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
-  [(set_attr "conds" "use")
-   (set_attr "length" "4,8")]
-)
-
 ; transform ((x << y) - 1) to ~(~(x-1) << y)  Where X is a constant.
 (define_split
   [(set (match_operand:SI 0 "s_register_operand" "")
@@ -1267,29 +1245,6 @@ 
    (set_attr "type" "simple_alu_imm,*,*")]
 )
 
-(define_expand "decscc"
-  [(set (match_operand:SI            0 "s_register_operand" "=r,r")
-        (minus:SI (match_operand:SI  1 "s_register_operand" "0,?r")
-		  (match_operator:SI 2 "arm_comparison_operator"
-                   [(match_operand   3 "cc_register" "") (const_int 0)])))]
-  "TARGET_32BIT"
-  ""
-)
-
-(define_insn "*arm_decscc"
-  [(set (match_operand:SI            0 "s_register_operand" "=r,r")
-        (minus:SI (match_operand:SI  1 "s_register_operand" "0,?r")
-		  (match_operator:SI 2 "arm_comparison_operator"
-                   [(match_operand   3 "cc_register" "") (const_int 0)])))]
-  "TARGET_ARM"
-  "@
-   sub%d2\\t%0, %1, #1
-   mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
-  [(set_attr "conds" "use")
-   (set_attr "length" "*,8")
-   (set_attr "type" "simple_alu_imm,*")]
-)
-
 (define_expand "subsf3"
   [(set (match_operand:SF           0 "s_register_operand" "")
 	(minus:SF (match_operand:SF 1 "s_register_operand" "")