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: Submitter =
Kito Cheng
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| 207 patches
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Apply
«
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
Check -shared is available for pr87906's tesstcase
Check -shared is available for pr87906's tesstcase
- - - -
-
-
-
2019-07-31
Kito Cheng
New
Check -shared is available for tesstcases
Check -shared is available for tesstcases
- - - -
-
-
-
2019-08-01
Kito Cheng
New
Docs: Add doc for RISC-V vector intrinsics
Docs: Add doc for RISC-V vector intrinsics
- - - -
-
-
-
2023-04-18
Kito Cheng
New
Docs: Add vector register constarint for asm operands
Docs: Add vector register constarint for asm operands
- - - -
-
-
-
2023-04-27
Kito Cheng
New
Fix alignment for local variable [PR90811]
Fix alignment for local variable [PR90811]
- - - -
-
-
-
2020-03-27
Kito Cheng
New
Fix array-quals-1.c for RISC-V
Fix array-quals-1.c for RISC-V
- - - -
-
-
-
2021-01-06
Kito Cheng
New
Fix print_multilib_info when default arguments appear in the option list with '!'
Fix print_multilib_info when default arguments appear in the option list with '!'
- - - -
-
-
-
2020-11-26
Kito Cheng
New
PR middle-end/88345: Honor -falign-functions=N even optimized for size.
PR middle-end/88345: Honor -falign-functions=N even optimized for size.
- - 1 -
-
-
-
2022-10-07
Kito Cheng
New
PR target/91441 - Turn off -fsanitize=kernel-address if TARGET_ASAN_SHADOW_OFFSET is not implemente…
PR target/91441 - Turn off -fsanitize=kernel-address if TARGET_ASAN_SHADOW_OFFSET is not implemente…
- - - -
-
-
-
2019-08-16
Kito Cheng
New
PR target/93995 ICE in patch_jump_insn, at cfgrtl.c:1290 on riscv64-linux-gnu
PR target/93995 ICE in patch_jump_insn, at cfgrtl.c:1290 on riscv64-linux-gnu
- - - -
-
-
-
2020-03-03
Kito Cheng
New
PR target/96260 - KASAN should work even back-end not porting anything.
PR target/96260 - KASAN should work even back-end not porting anything.
- - - -
-
-
-
2020-07-22
Kito Cheng
New
PR target/96307: Fix KASAN option checking.
PR target/96307: Fix KASAN option checking.
- - - -
-
-
-
2020-10-05
Kito Cheng
New
PR target/96759 - Handle global variable assignment from misaligned structure/PARALLEL return value…
PR target/96759 - Handle global variable assignment from misaligned structure/PARALLEL return value…
- - - -
-
-
-
2020-09-10
Kito Cheng
New
PR target/98152: Checking python is available before using
PR target/98152: Checking python is available before using
- - - -
-
-
-
2020-12-06
Kito Cheng
New
PR target/98743: Fix ICE in convert_move for RISC-V
PR target/98743: Fix ICE in convert_move for RISC-V
- - - -
-
-
-
2021-02-01
Kito Cheng
New
PR target/98878 - Incorrect multilib list for riscv*-rtems
PR target/98878 - Incorrect multilib list for riscv*-rtems
- - - -
-
-
-
2021-02-04
Kito Cheng
New
PR target/99314: Fix integer signedness issue for cpymem pattern expansion.
PR target/99314: Fix integer signedness issue for cpymem pattern expansion.
- - - -
-
-
-
2021-03-05
Kito Cheng
New
RISC-V: Add configure option: --with-multilib-config to flexible config multi-lib settings.
RISC-V: Add configure option: --with-multilib-config to flexible config multi-lib settings.
- - - -
-
-
-
2020-10-16
Kito Cheng
New
RISC-V: Add h extension support
RISC-V: Add h extension support
- - - -
-
-
-
2022-10-24
Kito Cheng
New
RISC-V: Add missing torture-init and torture-finish for rvv.exp
RISC-V: Add missing torture-init and torture-finish for rvv.exp
- - - -
-
-
-
2023-05-22
Kito Cheng
New
RISC-V: Add new option -march=help to print all supported extensions
RISC-V: Add new option -march=help to print all supported extensions
- - 1 -
-
-
-
2024-02-15
Kito Cheng
New
RISC-V: Add support for -mcpu option.
RISC-V: Add support for -mcpu option.
- - - -
-
-
-
2020-10-13
Kito Cheng
New
RISC-V: Add testcase for testing li pseudo instruction
RISC-V: Add testcase for testing li pseudo instruction
- - - -
-
-
-
2019-08-23
Kito Cheng
New
RISC-V: Adjust floating point code gen for LTGT compare
RISC-V: Adjust floating point code gen for LTGT compare
- - - -
-
-
-
2020-02-19
Kito Cheng
New
RISC-V: Allow multi-lib build with different code model
RISC-V: Allow multi-lib build with different code model
- - - -
-
-
-
2021-07-21
Kito Cheng
New
RISC-V: Always define MULTILIB_DEFAULTS
RISC-V: Always define MULTILIB_DEFAULTS
- - - -
-
-
-
2020-11-20
Kito Cheng
New
RISC-V: Always pass -misa-spec to assembler [PR104219]
RISC-V: Always pass -misa-spec to assembler [PR104219]
- - - -
-
-
-
2022-01-25
Kito Cheng
New
RISC-V: Basic VLS code gen for RISC-V
RISC-V: Basic VLS code gen for RISC-V
- - - -
-
-
-
2023-05-30
Kito Cheng
New
RISC-V: Canonicalize --with-arch
RISC-V: Canonicalize --with-arch
- - - -
-
-
-
2020-12-01
Kito Cheng
New
RISC-V: Check if zcd conflicts with zcmt and zcmp
RISC-V: Check if zcd conflicts with zcmt and zcmp
- - - -
-
-
-
2023-12-04
Kito Cheng
New
RISC-V: Define __riscv_cmodel_medany for PIC mode.
RISC-V: Define __riscv_cmodel_medany for PIC mode.
- - - -
-
-
-
2020-09-25
Kito Cheng
New
RISC-V: Define __riscv_v_intrinsic [PR109312]
RISC-V: Define __riscv_v_intrinsic [PR109312]
- - - -
-
-
-
2023-03-28
Kito Cheng
New
RISC-V: Derive ABI from -march if -mabi is not present.
RISC-V: Derive ABI from -march if -mabi is not present.
- - - -
-
-
-
2020-10-06
Kito Cheng
New
RISC-V: Disable remove unneeded save-restore call optimization if there are any arguments on stack.
RISC-V: Disable remove unneeded save-restore call optimization if there are any arguments on stack.
- - - -
-
-
-
2020-07-07
Kito Cheng
New
RISC-V: Disallow regrenme if the TO register never used before for interrupt functions
RISC-V: Disallow regrenme if the TO register never used before for interrupt functions
- - - -
-
-
-
2020-01-20
Kito Cheng
New
RISC-V: Documnet the list of supported extensions
RISC-V: Documnet the list of supported extensions
- - - -
-
-
-
2024-01-11
Kito Cheng
New
RISC-V: Emit .note.GNU-stack for non-linux target as well
RISC-V: Emit .note.GNU-stack for non-linux target as well
- - - -
-
-
-
2023-08-31
Kito Cheng
New
RISC-V: Extend syntax for the multilib-generator
RISC-V: Extend syntax for the multilib-generator
- - - -
-
-
-
2020-10-16
Kito Cheng
New
RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]
RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]
- - - -
-
-
-
2020-06-15
Kito Cheng
New
RISC-V: Fix RVV related testsuite
RISC-V: Fix RVV related testsuite
- - - -
-
-
-
2022-11-06
Kito Cheng
New
RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64
RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64
- - 1 -
-
-
-
2024-02-28
Kito Cheng
New
RISC-V: Fix compilation failed for frflags builtin in C++ mode
RISC-V: Fix compilation failed for frflags builtin in C++ mode
- - - -
-
-
-
2020-06-19
Kito Cheng
New
RISC-V: Fix misaligned stack offset for interrupt function
RISC-V: Fix misaligned stack offset for interrupt function
- - - -
-
-
-
2023-12-25
Kito Cheng
New
RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.
RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.
- - - -
-
-
-
2023-10-03
Kito Cheng
New
RISC-V: Handle different sigcontext struct layout.
RISC-V: Handle different sigcontext struct layout.
- - - -
-
-
-
2022-01-18
Kito Cheng
New
RISC-V: Handle extensions combination correctly in multilib-generator.
RISC-V: Handle extensions combination correctly in multilib-generator.
- - - -
-
-
-
2019-08-05
Kito Cheng
New
RISC-V: Handle g extension in multilib-generator
RISC-V: Handle g extension in multilib-generator
- - - -
-
-
-
2019-08-06
Kito Cheng
New
RISC-V: Handle multi-letter extension for multilib-generator
RISC-V: Handle multi-letter extension for multilib-generator
- - - -
-
-
-
2020-06-30
Kito Cheng
New
RISC-V: Handle multi-lib path correclty for linux
RISC-V: Handle multi-lib path correclty for linux
- - - -
-
-
-
2023-05-04
Kito Cheng
New
RISC-V: Handle rouding mode correctly on zfinx
RISC-V: Handle rouding mode correctly on zfinx
- - - -
-
-
-
2023-07-05
Kito Cheng
New
RISC-V: Handle vlenb correctly in unwinding
RISC-V: Handle vlenb correctly in unwinding
- - - -
-
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-
2023-02-12
Kito Cheng
New
RISC-V: Implment __builtin_thread_pointer
RISC-V: Implment __builtin_thread_pointer
- - - -
-
-
-
2020-07-07
Kito Cheng
New
RISC-V: Improve vector_insn_info::dump for LMUL and policy
RISC-V: Improve vector_insn_info::dump for LMUL and policy
- - - -
-
-
-
2023-05-12
Kito Cheng
New
RISC-V: Normalize arch string in driver time
RISC-V: Normalize arch string in driver time
- - - -
-
-
-
2020-06-19
Kito Cheng
New
RISC-V: Preserve arch version info during normalizing arch string
RISC-V: Preserve arch version info during normalizing arch string
- - - -
-
-
-
2020-06-30
Kito Cheng
New
RISC-V: Promote type correctly for libcalls
RISC-V: Promote type correctly for libcalls
- - - -
-
-
-
2019-08-01
Kito Cheng
New
RISC-V: Return const ref. for vl_vtype_info::get_avl_info
RISC-V: Return const ref. for vl_vtype_info::get_avl_info
- - - -
-
-
-
2022-12-27
Kito Cheng
New
RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC
RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC
- - - -
-
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-
2023-07-31
Kito Cheng
New
RISC-V: Save/restore ra register correctly [PR112478]
RISC-V: Save/restore ra register correctly [PR112478]
- - 1 1
-
-
-
2023-11-14
Kito Cheng
New
RISC-V: Support --target-help for -mcpu/-mtune
RISC-V: Support --target-help for -mcpu/-mtune
- - - -
-
-
-
2022-09-30
Kito Cheng
New
RISC-V: Tweak the wording for the sorry message
RISC-V: Tweak the wording for the sorry message
- - - -
-
-
-
2024-01-19
Kito Cheng
New
RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x
RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x
- - - -
-
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-
2020-02-18
Kito Cheng
New
Respect user align for local variable
Respect user align for local variable
- - - -
-
-
-
2020-03-30
Kito Cheng
New
[1/2] Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.
New target hook TARGET_COMPUTE_MULTILIB and implementation for RISC-V
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-
-
-
2021-07-21
Kito Cheng
New
[1/2] Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.
[1/2] Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.
- - - -
-
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-
2020-12-01
Kito Cheng
New
[1/2] Move out increase_alignment into ipa-increase-alignment.cc
[1/2] Move out increase_alignment into ipa-increase-alignment.cc
- - - -
-
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2020-03-27
Kito Cheng
New
[1/2] RISC-V: Allow extension name contain digit
RISC-V: Vector extensions support
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-
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-
2021-12-03
Kito Cheng
New
[1/2] RISC-V: Describe correct USEs for gpr_save pattern [PR95252]
[1/2] RISC-V: Describe correct USEs for gpr_save pattern [PR95252]
- - - -
-
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2020-06-10
Kito Cheng
New
[1/2] RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h
RISC-V: Introduce new architecture extension test macros
- - - -
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2021-01-04
Kito Cheng
New
[1/2] RISC-V: Support _Float16 type.
RISC-V: Support IEEE half precision operation
- - - -
-
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-
2022-07-07
Kito Cheng
New
[1/2] RISC-V: Update march parser
[1/2] RISC-V: Update march parser
- - - -
-
-
-
2020-03-31
Kito Cheng
New
[1/3] RISC-V: Handle implied extension in canonical ordering.
RISC-V: Support version controling for ISA standard extensions
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-
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2020-11-13
Kito Cheng
New
[1/3] RISC-V: Handle implied extension in canonical ordering.
[1/3] RISC-V: Handle implied extension in canonical ordering.
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-
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2020-11-13
Kito Cheng
New
[1/5] RISC-V: Extract part parsing base ISA logic into a standalone function [NFC]
RISC-V: Relax the -march string for accept any order
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-
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2024-01-08
Kito Cheng
New
[2/2] Fix alignment for local variable [PR90811]
[1/2] Move out increase_alignment into ipa-increase-alignment.cc
- - - -
-
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2020-03-27
Kito Cheng
New
[2/2] RISC-V: Handle implied extension for -march parser.
[1/2] RISC-V: Update march parser
- - - -
-
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-
2020-03-31
Kito Cheng
New
[2/2] RISC-V: Implement TARGET_COMPUTE_MULTILIB
New target hook TARGET_COMPUTE_MULTILIB and implementation for RISC-V
- - - -
-
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2021-07-21
Kito Cheng
New
[2/2] RISC-V: Implement TARGET_COMPUTE_MULTILIB
[1/2] Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.
- - - -
-
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-
2020-12-01
Kito Cheng
New
[2/2] RISC-V: Implement new style of architecture extension test macros.
RISC-V: Introduce new architecture extension test macros
- - - -
-
-
-
2021-01-04
Kito Cheng
New
[2/2] RISC-V: Minimal support of vector extensions
RISC-V: Vector extensions support
- - - -
-
-
-
2021-12-03
Kito Cheng
New
[2/2] RISC-V: Support zfh and zfhmin extension
RISC-V: Support IEEE half precision operation
- - - -
-
-
-
2022-07-07
Kito Cheng
New
[2/2] RISC-V: Unify the output asm pattern between gpr_save and gpr_restore pattern.
[1/2] RISC-V: Describe correct USEs for gpr_save pattern [PR95252]
- - - -
-
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-
2020-06-10
Kito Cheng
New
[2/3] RISC-V: Support zicsr and zifencei extension for -march.
RISC-V: Support version controling for ISA standard extensions
- - - -
-
-
-
2020-11-13
Kito Cheng
New
[2/3] RISC-V: Support zicsr and zifencei extension for -march.
[1/3] RISC-V: Handle implied extension in canonical ordering.
- - - -
-
-
-
2020-11-13
Kito Cheng
New
[2/5] RISC-V: Relax the -march string for accept any order
RISC-V: Relax the -march string for accept any order
- - - -
-
-
-
2024-01-08
Kito Cheng
New
[3/3] RISC-V: Support version controling for ISA standard extensions
RISC-V: Support version controling for ISA standard extensions
- - - -
-
-
-
2020-11-13
Kito Cheng
New
[3/3] RISC-V: Support version controling for ISA standard extensions
[1/3] RISC-V: Handle implied extension in canonical ordering.
- - - -
-
-
-
2020-11-13
Kito Cheng
New
[3/5] RISC-V: Remove unused function in riscv_subset_list [NFC]
RISC-V: Relax the -march string for accept any order
- - - -
-
-
-
2024-01-08
Kito Cheng
New
[4/5] RISC-V: Update testsuite due to -march string relaxation
RISC-V: Relax the -march string for accept any order
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-
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-
2024-01-08
Kito Cheng
New
[5/5] RISC-V: Document the syntax of -march
RISC-V: Relax the -march string for accept any order
- - - -
-
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-
2024-01-08
Kito Cheng
New
[PR/target,100316] Allow constant address for __builtin___clear_cache.
[PR/target,100316] Allow constant address for __builtin___clear_cache.
- - - -
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2021-10-07
Kito Cheng
New
[RFC,1/8] RISC-V: Minimal support of bitmanip extension
RISC-V: Bit-manipulation extension.
- - - -
-
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-
2021-09-23
Kito Cheng
New
[RFC,2/8] RISC-V: Implement instruction patterns for ZBA extension.
RISC-V: Bit-manipulation extension.
- - - -
-
-
-
2021-09-23
Kito Cheng
New
[RFC,3/8] RISC-V: Cost model for zba extension.
RISC-V: Bit-manipulation extension.
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2021-09-23
Kito Cheng
New
[RFC,4/8] RISC-V: Implement instruction patterns for ZBB extension.
RISC-V: Bit-manipulation extension.
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2021-09-23
Kito Cheng
New
[RFC,5/8] RISC-V: Cost model for zbb extension.
RISC-V: Bit-manipulation extension.
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2021-09-23
Kito Cheng
New
[RFC,6/8] RISC-V: Use li and rori to load constants.
RISC-V: Bit-manipulation extension.
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2021-09-23
Kito Cheng
New
[RFC,7/8] RISC-V: Implement instruction patterns for ZBS extension.
RISC-V: Bit-manipulation extension.
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2021-09-23
Kito Cheng
New
[RFC,8/8] RISC-V: Cost model for ZBS extension.
RISC-V: Bit-manipulation extension.
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2021-09-23
Kito Cheng
New
[committed,PR/target,102957] Allow Z*-ext extension with only 2 char.
[committed,PR/target,102957] Allow Z*-ext extension with only 2 char.
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2021-11-09
Kito Cheng
New
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