Show patches with: Submitter = Srinath Parvathaneni       |    State = Action Required       |    Archived = No       |   32 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[ARM] : Fix the failing ACLE testcase with correct test directive. [ARM] : Fix the failing ACLE testcase with correct test directive. - - - - 0 0 0 2019-11-21 Srinath Parvathaneni New
[ARM,14x] : MVE ACLE whole vector left shift with carry intrinsics. [ARM,14x] : MVE ACLE whole vector left shift with carry intrinsics. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,13x] : MVE ACLE scalar shift intrinsics. [ARM,13x] : MVE ACLE scalar shift intrinsics. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,12x] : MVE ACLE intrinsics to set and get vector lane. [ARM,12x] : MVE ACLE intrinsics to set and get vector lane. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,11x] : MVE ACLE vector interleaving store and deinterleaving load intrinsics and also aliase... [ARM,11x] : MVE ACLE vector interleaving store and deinterleaving load intrinsics and also aliase... - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,10x] : MVE ACLE intrinsics "add with carry across beats" and "beat-wise substract". [ARM,10x] : MVE ACLE intrinsics "add with carry across beats" and "beat-wise substract". - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,2/8x] : MVE ACLE gather load and scatter store intrinsics with writeback. [ARM,2/8x] : MVE ACLE gather load and scatter store intrinsics with writeback. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,7x] : MVE vreinterpretq and vuninitializedq intrinsics. [ARM,7x] : MVE vreinterpretq and vuninitializedq intrinsics. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,6x] :MVE ACLE vaddq intrinsics using arithmetic plus operator. [ARM,6x] :MVE ACLE vaddq intrinsics using arithmetic plus operator. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,7/5x] : MVE store intrinsics which stores byte,half word or word to memory. [ARM,7/5x] : MVE store intrinsics which stores byte,half word or word to memory. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,6/5x] : Remaining MVE load intrinsics which loads half word and word or double word from mem... [ARM,6/5x] : Remaining MVE load intrinsics which loads half word and word or double word from mem... - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,5/5x] : MVE ACLE load intrinsics which load a byte, halfword, or word from memory. [ARM,5/5x] : MVE ACLE load intrinsics which load a byte, halfword, or word from memory. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,4/5x] : MVE load intrinsics with zero(_z) suffix. [ARM,4/5x] : MVE load intrinsics with zero(_z) suffix. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,3/5x] : MVE store intrinsics with predicated suffix. [ARM,3/5x] : MVE store intrinsics with predicated suffix. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,2/5x] : MVE load intrinsics. [ARM,2/5x] : MVE load intrinsics. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,1/5x] : MVE store intrinsics. [ARM,1/5x] : MVE store intrinsics. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,1/4x] : MVE intrinsics with quaternary operands. [ARM,1/4x] : MVE intrinsics with quaternary operands. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,1/3x] : MVE intrinsics with ternary operands. [ARM,1/3x] : MVE intrinsics with ternary operands. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,3/2x] : MVE intrinsics with binary operands. [ARM,3/2x] : MVE intrinsics with binary operands. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,2/2x] : MVE intrinsics with binary operands. [ARM,2/2x] : MVE intrinsics with binary operands. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,1/2x] : MVE intrinsics with binary operands. [ARM,1/2x] : MVE intrinsics with binary operands. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,4/1x] : MVE intrinsics with unary operand. [ARM,4/1x] : MVE intrinsics with unary operand. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,2/1x] : MVE intrinsics with unary operand. [ARM,2/1x] : MVE intrinsics with unary operand. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,1/1x] : Patch to support MVE ACLE intrinsics with unary operand. [ARM,1/1x] : Patch to support MVE ACLE intrinsics with unary operand. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,4/x] : MVE ACLE vector interleaving store intrinsics. [ARM,4/x] : MVE ACLE vector interleaving store intrinsics. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,3/x] : MVE ACLE intrinsics framework patch. [ARM,3/x] : MVE ACLE intrinsics framework patch. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,2/x] : MVE ACLE intrinsics framework patch. [ARM,2/x] : MVE ACLE intrinsics framework patch. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[ARM,1/x] : MVE ACLE intrinsics framework patch. [ARM,1/x] : MVE ACLE intrinsics framework patch. - - - - 0 0 0 2019-11-14 Srinath Parvathaneni New
[GCC-7,AArch64] PR target/90075 Prefer bsl/bit/bif for copysignf. (backport GCC-7) [GCC-7,AArch64] PR target/90075 Prefer bsl/bit/bif for copysignf. (backport GCC-7) - - - - 0 0 0 2019-04-29 Srinath Parvathaneni New
[GCC-8,AArch64] PR target/90075 Prefer bsl/bit/bif for copysignf. (backport GCC-8) [GCC-8,AArch64] PR target/90075 Prefer bsl/bit/bif for copysignf. (backport GCC-8) - - - - 0 0 0 2019-04-29 Srinath Parvathaneni New
[2/2,ARM] Implement hint intrinsics for ARM [1/2,AArch64] Implement hint intrinsics for AArch64 - - - - 0 0 0 2019-01-10 Srinath Parvathaneni New
[1/2,AArch64] Implement hint intrinsics for AArch64 [1/2,AArch64] Implement hint intrinsics for AArch64 - - - - 0 0 0 2019-01-10 Srinath Parvathaneni New